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    VOLTAGE TRIMMING CIRCUIT
    23.
    发明公开
    VOLTAGE TRIMMING CIRCUIT 审中-公开

    公开(公告)号：US20230410925A1

    公开(公告)日：2023-12-21

    申请号：US18239548

    申请日：2023-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minho Choi ,  Jaeseong Lim ,  Kyungryun Kim ,  Daehyun Kim ,  Wonil Bae ,  Hohyun Shin ,  Sanghoon Jung ,  Hyongryol Hwang

    IPC: G11C17/18 ,  G11C29/08 ,  G11C17/16

    CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/08

    Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

    Memory device and an operating method thereof
    25.
    发明授权
    Memory device and an operating method thereof 有权

    公开(公告)号：US11551729B2

    公开(公告)日：2023-01-10

    申请号：US17215914

    申请日：2021-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangyun Kim ,  Kyungryun Kim ,  Junghwan Park ,  Yeonkyu Choi

    IPC: G11C11/34 ,  G11C5/14 ,  G11C7/22 ,  G11C7/06

    Abstract: A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    26.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11450396B2

    公开(公告)日：2022-09-20

    申请号：US17398434

    申请日：2021-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

    IPC: G11C29/18 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12

    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

    VOLTAGE TRIMMING CIRCUIT
    27.
    发明申请
    VOLTAGE TRIMMING CIRCUIT 有权

    公开(公告)号：US20220284975A1

    公开(公告)日：2022-09-08

    申请号：US17591987

    申请日：2022-02-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minho Choi ,  Jaeseong Lim ,  Kyungryun Kim ,  Daehyun Kim ,  Wonil Bae ,  Hohyun Shin ,  Sanghoon Jung ,  Hyongryol Hwang

    IPC: G11C17/18 ,  G11C17/16 ,  G11C29/08

    Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    29.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220020445A1

    公开(公告)日：2022-01-20

    申请号：US17398434

    申请日：2021-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

    IPC: G11C29/18 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44

    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

    Memory devices performing repair operations and repair operation methods thereof
    30.
    发明授权
    Memory devices performing repair operations and repair operation methods thereof 有权

    公开(公告)号：US11037653B2

    公开(公告)日：2021-06-15

    申请号：US16593023

    申请日：2019-10-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungryun Kim

    IPC: G11C7/00 ,  G11C29/00 ,  G11C8/10

    Abstract: A memory device includes: a memory cell array including a plurality of memory regions, the plurality of memory regions including first and second edge memory regions each respectively including an edge word line, and the plurality of memory regions including a center memory region including a center word line; a segment selection circuit configured to select a target segment from among a plurality of segments based on an input row address and output segment information identifying the target segment, where the first and second edge memory regions and the center memory region are grouped into a first segment of the plurality of segments; and a column decoder configured to control a column repair operation performed on a segment basis based on at least one fuse set that is selected based on the segment information.

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