公开(公告)号：US20160357485A1

公开(公告)日：2016-12-08

申请号：US15245000

申请日：2016-08-23

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Ning Chen ,  Erich F. Haratsch ,  Zhengang Chen

IPC: G06F3/06 ,  H03M13/00 ,  G11C29/52 ,  H03M13/37 ,  G11C16/08 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7205 ,  G11C16/08 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/3746 ,  H03M13/6505

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于在固态存储器中回收数据的系统和方法。 所述系统和方法包括接收保存在存储器件中的数据集，将数据解码算法的至少一次迭代应用于数据解码器电路的数据集，以产生解码输出，对数据解码算法的迭代次数进行计数 应用于数据集以产生迭代计数，并将数据集再循环到存储器件。 至少部分地基于迭代次数来触发回收。

公开(公告)号：US09459956B2

公开(公告)日：2016-10-04

申请号：US13958162

申请日：2013-08-02

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Alexander Hubris ,  Zhengang Chen ,  AbdelHakim S. Alhussien ,  YingQuan Wu

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/1048 ,  G06F11/10 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1142 ,  H03M13/116 ,  H03M13/1171 ,  H03M13/6561 ,  H03M13/658

Abstract: A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.

Abstract translation: 低密度奇偶校验解码器包括可变节点处理器，其可操作以生成可变节点以校验节点消息，并且基于对可变节点消息的校验节点来计算感知值;校验节点处理器，可操作以将校验节点生成到可变节点消息向量;以及 基于变量节点来计算校验和以检查节点消息;以及收敛检测器和位图生成器，其可操作用于感知值的收敛并生成至少一个位图，其识别连接到具有不满足奇偶校验检查的节点的变量节点 。

公开(公告)号：US09424179B2

公开(公告)日：2016-08-23

申请号：US14072530

申请日：2013-11-05

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Ning Chen ,  Erich F. Haratsch ,  Zhengang Chen

IPC: G06F12/02 ,  G06F11/10 ,  H03M13/11 ,  H03M13/00

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7205 ,  G11C16/08 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/3746 ,  H03M13/6505

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于在固态存储器中回收数据的系统和方法。 所述系统和方法包括接收保存在存储器件中的数据集，将数据解码算法的至少一次迭代应用于数据解码器电路的数据集，以产生解码输出，对数据解码算法的迭代次数进行计数 应用于数据集以产生迭代计数，并将数据集再循环到存储器件。 至少部分地基于迭代次数来触发回收。

公开(公告)号：US09417797B2

公开(公告)日：2016-08-16

申请号：US14299195

申请日：2014-06-09

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan ,  Yunxiang Wu

IPC: G11C16/28 ,  G06F3/06 ,  G11C16/26

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/28

Abstract: An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.

Abstract translation: 由闪存系统执行的自适应信道跟踪算法获得视差度量和导数度量，并且使用视差和微分度量的组合来估计最佳读取参考电压。 最佳读取参考电压的估计不依赖于下面的单元电压分布的假设，并导致读取参考电压的良好估计，即使单元电压分布的标准偏差不同。 此外，与已知的跟踪算法相比，该算法相对简单，计算量较少。

公开(公告)号：US20150355838A1

公开(公告)日：2015-12-10

申请号：US14299195

申请日：2014-06-09

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan ,  Yunxiang Wu

IPC: G06F3/06 ,  G11C16/28

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/28

Abstract: An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.

Abstract translation: 由闪存系统执行的自适应信道跟踪算法获得视差度量和导数度量，并且使用视差和微分度量的组合来估计最佳读取参考电压。 最佳读取参考电压的估计不依赖于下面的单元电压分布的假设，并导致读取参考电压的良好估计，即使单元电压分布的标准偏差不同。 此外，与已知的跟踪算法相比，该算法相对简单，计算量较少。

公开(公告)号：US20190385694A1

公开(公告)日：2019-12-19

申请号：US16552422

申请日：2019-08-27

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  David Patmore ,  Yingji Ju ,  Erich F. Haratsch

IPC: G11C29/42 ,  G11C29/36 ,  G11C29/44 ,  H03M13/11

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

公开(公告)号：US10388385B2

公开(公告)日：2019-08-20

申请号：US15440225

申请日：2017-02-23

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan

IPC: G06F3/06 ,  G06F11/14 ,  G11C16/28 ,  G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C29/02 ,  G11C7/14

Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.

公开(公告)号：US09941901B2

公开(公告)日：2018-04-10

申请号：US15055006

申请日：2016-02-26

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Zhengang Chen ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: H03M13/11 ,  G06F11/10 ,  G11C29/52

CPC classification number: H03M13/1111 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1072 ,  G11C29/52 ,  H03M13/1154

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.

公开(公告)号：US09916906B2

公开(公告)日：2018-03-13

申请号：US14198862

申请日：2014-03-06

Applicant: Seagate Technology LLC

Inventor： Yunxiang Wu ,  Yu Cai ,  Zhengang Chen ,  Erich Haratsch

IPC: G11C7/14 ,  G11C29/52 ,  G11C29/04 ,  G11C29/02 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G11C29/50

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/1072 ,  G06F2212/403 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Log likelihood ration (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.

公开(公告)号：US20170322750A1

公开(公告)日：2017-11-09

申请号：US15659267

申请日：2017-07-25

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Ning Chen ,  Erich F. Haratsch ,  Zhengang Chen

IPC: G06F3/06 ,  H03M13/37 ,  H03M13/11 ,  G11C29/52 ,  G11C16/08 ,  G06F12/02 ,  G06F11/10 ,  H03M13/00

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7205 ,  G11C16/08 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/3746 ,  H03M13/6505

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.