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公开(公告)号:US11545230B2
公开(公告)日:2023-01-03
申请号:US16552422
申请日:2019-08-27
Applicant: Seagate Technology LLC
Inventor: Zhengang Chen , David Patmore , Yingji Ju , Erich F. Haratsch
IPC: G11C29/42 , G11C29/44 , G11C29/36 , H03M13/11 , H04L1/00 , G06F11/00 , G11C7/10 , G06F3/06 , G11C11/56 , G11C29/52 , G11C16/10 , G11C16/00
Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
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公开(公告)号:US20150262712A1
公开(公告)日:2015-09-17
申请号:US14223407
申请日:2014-03-24
Applicant: Seagate Technology LLC
Inventor: Zhengang Chen , David Patmore , Yingji JU , Erich F. Haratsch
IPC: G11C29/44
CPC classification number: G11C29/42 , G06F11/00 , G11C7/10 , G11C16/00 , G11C29/36 , G11C29/44 , H03M13/1108 , H04L1/00
Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to blocks of the memory that are not marked as bad on a block list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to perform a plurality of scans on the memory. The scans are configured to (a) identify the bad blocks, and (b) mark the bad blocks as bad on the block list.
Abstract translation: 一种包括存储器和控制器的装置。 存储器被配置为处理多个读/写操作。 存储器包括多个存储器模块,每个存储器模块的尺寸小于存储器的总大小。 控制器被配置为处理对块列表中未被标记为不良的存储器块的多个I / O请求。 控制器被配置为跟踪存储器的多个坏块。 控制器被配置为对存储器执行多次扫描。 扫描被配置为(a)识别坏块,并且(b)将坏块标记在块列表上是不好的。
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公开(公告)号:US10410736B2
公开(公告)日:2019-09-10
申请号:US15423692
申请日:2017-02-03
Applicant: Seagate Technology LLC
Inventor: Zhengang Chen , David Patmore , Yingji Ju , Erich F. Haratsch
IPC: G11C29/42 , G11C29/44 , G11C29/36 , H03M13/11 , H04L1/00 , G06F11/00 , G11C7/10 , G06F3/06 , G11C11/56 , G11C29/52 , G11C16/10 , G11C16/00
Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
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公开(公告)号:US09595352B2
公开(公告)日:2017-03-14
申请号:US14223407
申请日:2014-03-24
Applicant: Seagate Technology LLC
Inventor: Zhengang Chen , David Patmore , Yingji Ju , Erich F. Haratsch
CPC classification number: G11C29/42 , G06F11/00 , G11C7/10 , G11C16/00 , G11C29/36 , G11C29/44 , H03M13/1108 , H04L1/00
Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to blocks of the memory that are not marked as bad on a block list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to perform a plurality of scans on the memory. The scans are configured to (a) identify the bad blocks, and (b) mark the bad blocks as bad on the block list.
Abstract translation: 一种包括存储器和控制器的装置。 存储器被配置为处理多个读/写操作。 存储器包括多个存储器模块,每个存储器模块的尺寸小于存储器的总大小。 控制器被配置为处理对块列表中未被标记为不良的存储器块的多个I / O请求。 控制器被配置为跟踪存储器的多个坏块。 控制器被配置为对存储器执行多次扫描。 扫描被配置为(a)识别坏块,并且(b)将坏块标记在块列表上是不好的。
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公开(公告)号:US20190385694A1
公开(公告)日:2019-12-19
申请号:US16552422
申请日:2019-08-27
Applicant: Seagate Technology LLC
Inventor: Zhengang Chen , David Patmore , Yingji Ju , Erich F. Haratsch
Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
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公开(公告)号:US20170148530A1
公开(公告)日:2017-05-25
申请号:US15423692
申请日:2017-02-03
Applicant: Seagate Technology LLC
Inventor: Zhengang Chen , David Patmore , Yingji Ju , Erich F. Haratsch
CPC classification number: G11C29/42 , G06F3/064 , G06F11/00 , G11C7/10 , G11C11/5628 , G11C16/00 , G11C16/10 , G11C29/36 , G11C29/44 , G11C29/52 , H03M13/1108 , H04L1/00
Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
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