中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.019 seconds)

    REGULATOR OF A SENSE AMPLIFIER
    24.
    发明申请
    REGULATOR OF A SENSE AMPLIFIER 有权

    公开(公告)号：US20230110870A1

    公开(公告)日：2023-04-13

    申请号：US17490976

    申请日：2021-09-30

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    Inventor： Laura Capecchi ,  Marcella Carissimi ,  Marco Pasotti ,  Vikas Rana ,  Vivek Tyagi

    IPC: G11C7/06 ,  G11C7/14

    Abstract: A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.

    Non-volatile memory device having a reading circuit operating at low voltage
    25.
    发明授权
    Non-volatile memory device having a reading circuit operating at low voltage 有权

    公开(公告)号：US11282573B2

    公开(公告)日：2022-03-22

    申请号：US16904869

    申请日：2020-06-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Davide Manfre′ ,  Laura Capecchi ,  Marcella Carissimi ,  Marco Pasotti

    IPC: G11C11/00 ,  G11C13/00

    Abstract: A non-volatile memory device includes a memory array, a reading circuit, a column decoder stage, and a read supply voltage generator. The column decoder stage includes selectable bitlines and selection switches. A read supply voltage generator includes a voltage regulation circuit and a dummy column decoder coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path. The voltage regulation circuit is configured to receive a first electrical quantity correlated to a desired voltage value on the selected bitline and a second electrical quantity correlated to a desired current value for the selected bitline and to generate a regulated read supply voltage for the column decoder stage.

    CURRENT-GENERATOR CIRCUIT
    27.
    发明申请
    CURRENT-GENERATOR CIRCUIT 有权

    公开(公告)号：US20210035637A1

    公开(公告)日：2021-02-04

    申请号：US16940837

    申请日：2020-07-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Laura Capecchi ,  Marco Pasotti ,  Marcella Carissimi ,  Riccardo Zurla

    IPC: G11C13/00 ,  G05F3/26

    Abstract: A current-generator circuit includes an output-current generator circuit having a control branch to be coupled to a control current generator and adapted to provide a control current pulse and a driver electrically coupled between the control branch and the output leg. A compensation circuit includes a first compensation branch configured to generate a compensation current pulse that is a function of the control current pulse and a second compensation branch coupled in a current mirror configuration with the first compensation branch to receive the compensation current pulse. The second compensation branch includes a resistive block having an electrical resistance that is a function of a resistance of an output load. The second compensation branch is electrically coupled to the control branch and the driver is electrically coupled to the control branch and to the output leg.

    LATCH-TYPE SENSE AMPLIFIER FOR A NON-VOLATILE MEMORY WITH REDUCED MARGIN BETWEEN SUPPLY VOLTAGE AND BITLINE-SELECTION VOLTAGE
    28.
    发明申请
    LATCH-TYPE SENSE AMPLIFIER FOR A NON-VOLATILE MEMORY WITH REDUCED MARGIN BETWEEN SUPPLY VOLTAGE AND BITLINE-SELECTION VOLTAGE 有权

    公开(公告)号：US20210020237A1

    公开(公告)日：2021-01-21

    申请号：US16931335

    申请日：2020-07-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marcella Carissimi ,  Laura Capecchi ,  Marco Pasotti ,  Fabio Enrico Carlo Disegni

    IPC: G11C13/00

    Abstract: A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.

    NONVOLATILE, ELECTRICALLY NON-PROGRAMMABLE MEMORY DEVICE AND MANUFACTORY PROCESS THEREOF
    29.
    发明申请
    NONVOLATILE, ELECTRICALLY NON-PROGRAMMABLE MEMORY DEVICE AND MANUFACTORY PROCESS THEREOF 审中-公开

    公开(公告)号：US20190130970A1

    公开(公告)日：2019-05-02

    申请号：US16169763

    申请日：2018-10-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marcella Carissimi ,  Marco Pasotti ,  Chantal Auricchio

    IPC: G11C13/00

    Abstract: The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.

    IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY
    30.
    发明申请
    IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20170200483A1

    公开(公告)日：2017-07-13

    申请号：US15471028

    申请日：2017-03-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

    IPC: G11C7/22 ,  G11C7/06

    CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

    Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.

Patent Agency Ranking