公开(公告)号：US20160155701A1

公开(公告)日：2016-06-02

申请号：US14557111

申请日：2014-12-01

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Yann Mignot ,  Terry Spooner ,  James John Kelly

IPC: H01L23/522 ,  H01L21/288 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/288 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes first and second metallization levels. The first metallization level includes a first metal routing path. The second metallization level includes a dielectric layer having a via opening formed therein extending vertically through the dielectric layer to reach a top surface of the first metal routing path. A metal plug is deposited at a bottom of the via opening in direct contact with the first metal routing path. A remaining open area of the via opening is filled with a metal material to define a second metal routing path. The metal plug is formed of cobalt or an alloy including cobalt, and has an aspect ratio of greater than 0.3.

Abstract translation: 集成电路包括第一和第二金属化层。 第一金属化层包括第一金属路由路径。 第二金属化层包括介电层，其具有形成在其中的通孔，所述通孔开口垂直延伸穿过电介质层，以到达第一金属路由路径的顶表面。 金属插塞沉积在与第一金属布线路径直接接触的通孔开口的底部。 通孔开口的剩余开口区域填充有金属材料以限定第二金属路由路径。 金属塞由钴或包括钴的合金形成，并且具有大于0.3的纵横比。

公开(公告)号：US20150162277A1

公开(公告)日：2015-06-11

申请号：US14098286

申请日：2013-12-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Yann Mignot ,  Lawrence A. Clevenger ,  Carl Radens ,  Richard Stephen Wise ,  Yiheng Xu ,  Yannick Loquet ,  Hsueh-Chung Chen

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/0217 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将气隙结合到高模量介电材料中以保持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的气隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 含有气隙的较高模量的膜用作相邻金属线之间的绝缘体，同时保留ULK膜以绝热通孔。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

公开(公告)号：US20150001735A1

公开(公告)日：2015-01-01

申请号：US14320326

申请日：2014-06-30

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Yann Mignot ,  Hsueh-Chung Chen

IPC: H01L23/522 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device an include forming an first low temperature oxide (LTO) layer over an organic planarization layer (OPL) layer, forming a primary via pattern in the LTO layer to partially expose the OPL layer, forming a conformal second LTO layer over the primary via pattern including the first LTO layer and the partially exposed OPL layer, and etching the second LTO layer to form spacers on sidewalls of the primary via pattern in the first LTO layer.

Abstract translation: 制造半导体器件的方法包括在有机平坦化层（OPL）层上形成第一低温氧化物（LTO）层，在LTO层中形成初级通孔图案以部分地曝光OPL层，形成保形第二LTO 在包括第一LTO层和部分曝光的OPL层的主通路图案之上，并且蚀刻第二LTO层以在第一LTO层中的主通孔图案的侧壁上形成间隔物。

公开(公告)号：US20180144926A1

公开(公告)日：2018-05-24

申请号：US15874654

申请日：2018-01-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Yann Mignot ,  Lawrence A. Clevenger ,  Carl Radens ,  Richard Stephen Wise ,  Yiheng Xu ,  Yannick Loquet ,  Hsueh-Chung Chen

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/0217 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

公开(公告)号：US20160379881A1

公开(公告)日：2016-12-29

申请号：US14751380

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ming He ,  Seowoo Nam ,  Yann Mignot ,  Jim Kelly ,  Raghuveer Patlotta ,  Theodorus Standaert

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/528

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在第一层间电介质中形成互连。 第一盖形成在与互连件相邻的第一层间电介质上，并且形成覆盖第一层间电介质，互连和盖的第二层间电介质。 通过第二层间电介质形成触点，其中触点包括重叠区域和连接区域。 重叠区域直接覆盖与互连件相邻的第一层间电介质，并且连接区域直接接触互连。 第一盖位于重叠区域和第一层间电介质之间。

公开(公告)号：US20160372334A1

公开(公告)日：2016-12-22

申请号：US14743511

申请日：2015-06-18

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Yann Mignot ,  Brown C. Peethala ,  Shariq Siddiqui

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/033

CPC classification number: H01L21/31116 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/76816

Abstract: A method that allows effective removal of a silicon-containing antireflective coating (SiARC) layer in a block mask after defining an unblock area in a sidewall image transfer (SIT) patterning process without causing a height loss of the SIT spacers is provided. The method includes first modifying the SiARC layer with a dry etch utilizing an etching gas comprising a nitrogen gas followed by treating the modified SiARC layer with a wet chemical etch utilizing an aqueous solution including dilute hydrofluoric acid and citric acid.

Abstract translation: 提供一种在限制了侧壁图像转印（SIT）图案化工艺中的未封闭区域而不引起SIT间隔物的高度损失之前有效去除块掩模中的含硅抗反射涂层（SiARC）层的方法。 该方法包括首先利用包含氮气的蚀刻气体进行干法蚀刻来修饰SiARC层，然后利用包含稀氢氟酸和柠檬酸的水溶液进行湿化学蚀刻来处理改性的SiARC层。

公开(公告)号：US09466563B2

公开(公告)日：2016-10-11

申请号：US14557111

申请日：2014-12-01

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Yann Mignot ,  Terry Spooner ,  James John Kelly

IPC: H01L21/44 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/288

CPC classification number: H01L23/5226 ,  H01L21/288 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes first and second metallization levels. The first metallization level includes a first metal routing path. The second metallization level includes a dielectric layer having a via opening formed therein extending vertically through the dielectric layer to reach a top surface of the first metal routing path. A metal plug is deposited at a bottom of the via opening in direct contact with the first metal routing path. A remaining open area of the via opening is filled with a metal material to define a second metal routing path. The metal plug is formed of cobalt or an alloy including cobalt, and has an aspect ratio of greater than 0.3.

Abstract translation: 集成电路包括第一和第二金属化层。 第一金属化层包括第一金属路由路径。 第二金属化层包括介电层，其具有形成在其中的通孔，所述通孔开口垂直延伸穿过电介质层，以到达第一金属路由路径的顶表面。 金属插塞沉积在与第一金属布线路径直接接触的通孔开口的底部。 通孔开口的剩余开口区域填充有金属材料以限定第二金属路由路径。 金属塞由钴或包括钴的合金形成，并且具有大于0.3的纵横比。

公开(公告)号：US09252051B1

公开(公告)日：2016-02-02

申请号：US14540367

申请日：2014-11-13

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Joe Lee ,  Yann Mignot ,  Douglas M. Trickett

IPC: H01L21/302 ,  H01L21/768

CPC classification number: H01L21/76819 ,  H01L21/76804 ,  H01L21/76811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: After completely etching through a material stack comprising an oxide hard mask layer and an underlying interlevel dielectric (ILD) layer formed on a substrate to provide at least one opening, top corners of the at least one opening are rounded by performing a plasma etch employing a combination of an etching gas and a deposition gas comprising a hydrofluorocarbon compound. The hydrofluorocarbon compound forms a hydrofluorocarbon polymer layer on sidewalls of the at least one opening and helps to preserve the profile of the at least one opening.

Abstract translation: 在通过包括氧化物硬掩模层和形成在衬底上的下面的层间电介质（ILD）层的材料堆完全蚀刻以提供至少一个开口之后，通过执行等离子体蚀刻来使至少一个开口的顶角变圆， 蚀刻气体和包含氢氟烃化合物的沉积气体的组合。 氢氟烃化合物在至少一个开口的侧壁上形成氢氟烃聚合物层，有助于保持至少一个开口的轮廓。