公开(公告)号：US20180097058A1

公开(公告)日：2018-04-05

申请号：US15444644

申请日：2017-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel ,  Alexandre Sarafianos

IPC: H01L29/06 ,  H03K5/24 ,  H01L29/10 ,  H01L27/06 ,  G06F21/77

CPC classification number: H01L29/0623 ,  G06F21/75 ,  G06F21/77 ,  G06F21/78 ,  G06F21/87 ,  G06F21/88 ,  H01L21/823892 ,  H01L23/57 ,  H01L23/576 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/66181 ,  H03K5/24

Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

公开(公告)号：US11942440B2

公开(公告)日：2024-03-26

申请号：US17091466

申请日：2020-11-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L23/00 ,  G06F21/55 ,  G06F21/78 ,  G06F21/87 ,  H01L29/06 ,  H04L9/00

CPC classification number: H01L23/576 ,  G06F21/556 ,  G06F21/78 ,  G06F21/87 ,  H01L29/0646 ,  H01L29/0649 ,  H04L9/004 ,  H04L2209/12

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.

公开(公告)号：US11189578B2

公开(公告)日：2021-11-30

申请号：US16409704

申请日：2019-05-10

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas ,  Daniele Fronte

IPC: H01L23/528 ,  H01L23/00 ,  G01N27/04 ,  H01L23/522

Abstract: The disclosure concerns an electronic chip including a resistive region and a first switch of selection of a first area in contact with the resistive region.

公开(公告)号：US10453808B2

公开(公告)日：2019-10-22

申请号：US16129163

申请日：2018-09-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L23/00 ,  H01L21/66 ,  H01L29/861 ,  H01L29/06

Abstract: An electronic integrated circuit includes a semiconductor substrate having a rear face. A device for detecting a thinning of the semiconductor substrate via its rear face is formed by a p-n junction that is biased into conduction. Thinning of the substrate is detected by monitoring a current flowing through the p-n junction, and comparing that current to a threshold. In the event the compared current indicates no thinning of the semiconductor substrate, the circuitry for biasing and comparing is deactivated.

公开(公告)号：US20190147771A1

公开(公告)日：2019-05-16

申请号：US16186820

申请日：2018-11-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge

IPC: G09C1/00 ,  H03K19/003

Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.

公开(公告)号：US20190122090A1

公开(公告)日：2019-04-25

申请号：US16227525

申请日：2018-12-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge ,  Jimmy Fort

IPC: G06K19/073 ,  G06F21/75 ,  G06F21/44 ,  H01L23/00

Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

公开(公告)号：US10198683B2

公开(公告)日：2019-02-05

申请号：US15798553

申请日：2017-10-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas ,  Yanis Linge ,  Jimmy Fort

IPC: G06K19/073 ,  G06F21/75 ,  G06F21/44 ,  H01L23/00 ,  H03K19/173 ,  H03K17/693

Abstract: An electronic device randomly modifies a current profile of a logic circuit by using an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

公开(公告)号：US10063239B2

公开(公告)日：2018-08-28

申请号：US15627157

申请日：2017-06-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas

IPC: H03K19/00 ,  G01T1/24 ,  H03K19/177 ,  H01L23/00 ,  H03K19/003 ,  G06F21/75 ,  G06F21/87

CPC classification number: H03K19/17768 ,  G06F21/75 ,  G06F21/87 ,  G09C1/00 ,  H01L23/576 ,  H03K19/0033 ,  H03K19/17704 ,  H04L9/004 ,  H04L2209/12

Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.

公开(公告)号：US20180094973A1

公开(公告)日：2018-04-05

申请号：US15444529

申请日：2017-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Clement Champeix

IPC: G01J1/44 ,  H01L31/112

CPC classification number: G01J1/44 ,  G01J2001/4238 ,  G06F21/87 ,  H01L23/576 ,  H01L31/03529 ,  H01L31/09 ,  H01L31/103 ,  H01L31/112

Abstract: A laser detection device can be used to protect an integrated circuit. The device includes a detection cell having a buried channel of a first conductivity type extending in a substrate of the integrated circuit. The substrate is of a second conductivity type. The detection cell also has a first electrical connection coupling a first point in the buried channel to a supply voltage rail, and a second electrical connection coupled to a second point in the buried channel. A detection circuit is coupled to the second point in the buried channel via the second electrical connection and adapted to detect a fall in the voltage at the second point.

公开(公告)号：US20180040574A1

公开(公告)日：2018-02-08

申请号：US15789362

申请日：2017-10-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Mathieu Lisart ,  Jimmy Fort

IPC: H01L23/00 ,  H01L21/762

CPC classification number: H01L23/576 ,  H01L21/762 ,  H01L27/088

Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.