-
公开(公告)号：US10949572B2
公开(公告)日：2021-03-16
申请号：US16411819
申请日：2019-05-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Thomas Ordas , Yanis Linge , Jimmy Fort
IPC: G06F21/75 , H04L9/00 , G06F30/327
Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.
-
公开(公告)号：US10560089B2
公开(公告)日：2020-02-11
申请号：US16161531
申请日：2018-10-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas Borrel , Jimmy Fort , Francesco La Rosa
Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.
-
公开(公告)号：US20180189624A1
公开(公告)日：2018-07-05
申请号：US15798553
申请日：2017-10-31
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Thomas Ordas , Yanis Linge , Jimmy Fort
IPC: G06K19/073 , H01L23/00 , G06F21/44
CPC classification number: G06K19/07363 , G06F21/445 , G06F21/75 , G06F21/755 , H01L23/576 , H01L2224/48228
Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
-
公开(公告)号：US09836070B2
公开(公告)日：2017-12-05
申请号：US14937671
申请日：2015-11-10
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Jimmy Fort , Thierry Soude
CPC classification number: G05F1/575 , H03F3/45179
Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.
-
公开(公告)号：US20170116439A1
公开(公告)日：2017-04-27
申请号：US15137789
申请日：2016-04-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Jimmy Fort , Clement Champeix , Jean-Max Dutertre , Nicolas Borrel
CPC classification number: G06F21/86 , G09C1/00 , H01L23/576 , H03K5/153 , H03K5/24 , H04L9/004 , H04L2209/12
Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.
-
Patent Agency Ranking
公开(公告)号：US09454163B2
公开(公告)日：2016-09-27
申请号：US14612063
申请日：2015-02-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Thierry Soude
Abstract: According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.
-
27.发明申请公开(公告)号：US20150145487A1
公开(公告)日：2015-05-28
申请号：US14612063
申请日：2015-02-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Thierry Soude
IPC: G05F1/46
Abstract: According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.
Abstract translation: 根据实施例，产生可调节带隙参考电压包括产生与绝对温度（PTAT）成比例的电流。 产生PTAT电流包括跨越由PTAT电流穿过的芯的端子的均衡电压。 生成可调节带隙基准还包括产生与绝对温度（CTAT）成反比的电流，对PTAT和CTAT电流求和，并根据电流之和产生带隙基准电压。 均衡包括将核心的端子连接到具有布置为折叠设置的至少一个第一级的第一反馈放大器，并且包括根据公共门设置布置的第一PMOS晶体管。 均衡还包括基于CTAT电流偏置第一阶段。 在第一放大器的反馈级中执行PTAT和CTAT电流的求和。
-
28.发明授权公开(公告)号：US11768512B2
公开(公告)日：2023-09-26
申请号：US17119788
申请日：2020-12-11
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Nicolas Demange
Abstract: An embodiment method for smoothing consumed current is based on a current copying suite and on a current source supplying a reference current, the currents being transformed into a reference voltage for the regulation of a voltage regulator such that the consumed current viewed by the power supply only depends on the reference current.
-
公开(公告)号：US11698651B2
公开(公告)日：2023-07-11
申请号：US17399674
申请日：2021-08-11
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas Demange , Nicolas Borrel , Jimmy Fort
CPC classification number: G05F1/56 , G06F21/755
Abstract: The present invention concerns an electronic circuit power supply device, configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node, a first branch of a current mirror conducting the third current; flow a fourth constant current through a third conductor connected to the node; consume a fifth current that is an image of the third current; and regulate a potential of the node by acting on a gate potential of a transistor electrically in series with a second branch of the current mirror.
-
公开(公告)号：US11626862B2
公开(公告)日：2023-04-11
申请号：US17251738
申请日：2019-06-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Tramoni , Jimmy Fort
IPC: G06F1/3287 , H03K3/0233 , H03K17/687
Abstract: An embodiment of the present disclosure relates to a circuit of cyclic activation of an electronic function comprising a hysteresis comparator controlling the charge of a capacitive element powering the function.
-
-
-
-
-
-
-
-
-
Search Results
56
records
(took 0.02 seconds)
