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    Resistive memory cell having a compact structure
    24.
    发明授权
    Resistive memory cell having a compact structure 有权

    公开(公告)号：US10283563B2

    公开(公告)日：2019-05-07

    申请号：US15694463

    申请日：2017-09-01

    Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

    Inventor： Philippe Boivin ,  Simon Jeannot

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

    METHOD OF FABRICATING A VERTICAL MOS TRANSISTOR
    27.
    发明申请
    METHOD OF FABRICATING A VERTICAL MOS TRANSISTOR 有权
    制造垂直MOS晶体管的方法

    公开(公告)号：US20140191178A1

    公开(公告)日：2014-07-10

    申请号：US14150592

    申请日：2014-01-08

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Philippe Boivin

    IPC: H01L27/24 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/2257 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10876 ,  H01L27/2454 ,  H01L29/0676 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

    Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.

    Abstract translation: 本发明涉及一种制造垂直MOS晶体管的方法，包括以下步骤：在半导体表面之上形成至少一个电介质层中的导电层; 通过至少导电层蚀刻孔，所述孔暴露所述导电层的内侧边缘和所述半导体表面的一部分; 在导电层的内侧边缘上形成栅极氧化物，在半导体表面的部分上形成底部氧化物; 在所述孔的侧边缘上形成蚀刻保护侧壁，所述侧壁覆盖所述栅极氧化物和所述底部氧化物的外部区域，留下所述底部氧化物的内部区域; 蚀刻底部氧化物的暴露的内部区域，直到达到半导体表面; 以及在所述孔中沉积半导体材料。

    Insulation of phase-change memory cells
    28.
    发明授权
    Insulation of phase-change memory cells 有权

    公开(公告)号：US12213392B2

    公开(公告)日：2025-01-28

    申请号：US17362670

    申请日：2021-06-29

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Philippe Boivin

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

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