公开(公告)号：US20190172782A1

公开(公告)日：2019-06-06

申请号：US16269300

申请日：2019-02-06

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/10 ,  H05K3/20 ,  H01L23/00 ,  H05K3/40 ,  H01L21/48

Abstract: A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.

公开(公告)号：US20180190564A1

公开(公告)日：2018-07-05

申请号：US15617561

申请日：2017-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/552 ,  H01L23/495 ,  H01L21/56 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/373 ,  H01L21/288 ,  H01L21/32055 ,  H01L21/4875 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/552 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/73265

Abstract: A semiconductor device, such as a semiconductor power device, includes: a semiconductor die having a semiconductor die front surface, a package formed onto the semiconductor die, the package having a portion facing the front surface of the semiconductor die, and a thermally-conductive layer including graphene over the front portion of the package facing the front surface of the semiconductor die.

公开(公告)号：US20180114778A1

公开(公告)日：2018-04-26

申请号：US15842650

申请日：2017-12-14

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: An integrated circuit package with improved reliability and methods for creating the same are disclosed. More specifically, integrated circuit packages are created using one or more sacrificial layers that provide support for ink printed wires prior to package processing, but are removed during package processing. Once each of the sacrificial layers is removed, molding compound is placed around each ink printed wire, which may have a substantially rectangular cross section that can vary in dimension along a length of a given wire. While substantially surrounding each wire in and of itself improves reliability, removing non-conductive paste, fillets, or other adhesive materials also minimizes adhesion issues between the molding compound and those materials, which increases the bond of the molding compound to the package and its components. The net result is a more reliable integrated circuit package that is less susceptible to internal cracking and wire damage.

公开(公告)号：US20170338170A1

公开(公告)日：2017-11-23

申请号：US15159604

申请日：2016-05-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/49565 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed. In one embodiment, the wettable conductive layers are printed on the package body and the leads by Aerosol Jet® technology.

公开(公告)号：US20170053888A1

公开(公告)日：2017-02-23

申请号：US15134743

申请日：2016-04-21

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L23/00

CPC classification number: H01L23/3135 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48997 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/8584 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2924/40102 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/43848

Abstract: A method is for making a semiconductor device having an IC die on a substrate with electric contact formations for the IC die and the substrate. The method may include printing ink including electrically conductive nanoparticles, onto the electric contact formations.

Abstract translation: 一种用于制造具有IC芯片的半导体器件的方法，该半导体器件具有用于IC管芯和衬底的电接触形成的衬底。 该方法可以包括印刷包含导电纳米颗粒的油墨到电接触层上。

公开(公告)号：US20140083206A1

公开(公告)日：2014-03-27

申请号：US14027990

申请日：2013-09-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Alberto PAGANI ,  Federico Giovanni ZIGLIOLI

IPC: G01L1/00

CPC classification number: G01L1/005 ,  G01N33/38 ,  H05K1/0239 ,  H05K1/0278 ,  H05K1/189 ,  H05K2201/09081 ,  H05K2201/10098 ,  H05K2201/10151 ,  Y10T156/1051

Abstract: A planar electric circuit board may include a planar support of a foldable material defining a base surface and wings coupled to the base surface along respective folding lines so that the wings, when folded along the folding lines, are erected with respect to the base surface and remain in that position. An auxiliary circuit is on the planar support and may include pairs of capacitive coupling plates defined on the wings and on the base surface, and electric communication lines coupled to corresponding ones of the pairs of capacitive coupling plates.

Abstract translation: 平面电路板可以包括限定基部表面的可折叠材料的平面支撑件和沿着各个折叠线连接到基座表面的翼片，使得当沿着折叠线折叠时的翼片相对于基部表面竖立，并且 保持在这个位置。 辅助电路在平面支撑件上，并且可以包括限定在翼部和基部表面上的成对的电容耦合板，以及耦合到成对的电容耦合板中的对应的电气通信线。