公开(公告)号：US12170322B2

公开(公告)日：2024-12-17

申请号：US17504720

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyuk Yim ,  Byounghak Hong ,  Jungsu Kim ,  Kang-ill Seo

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US12125788B2

公开(公告)日：2024-10-22

申请号：US18386497

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Gil Hwan Son ,  Byounghak Hong ,  Kang Ill Seo

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0694 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

公开(公告)号：US12087815B2

公开(公告)日：2024-09-10

申请号：US18187506

申请日：2023-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwichan Jun ,  Inchan Hwang ,  Byounghak Hong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.

公开(公告)号：US12057448B2

公开(公告)日：2024-08-06

申请号：US18356545

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US20230420459A1

公开(公告)日：2023-12-28

申请号：US18056181

申请日：2022-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Sooyoung Park ,  Jaehong Lee ,  Kang-ill Seo ,  WookHyun Kwon

IPC: H01L27/092 ,  H01L27/06 ,  H01L21/768

CPC classification number: H01L27/0922 ,  H01L27/0688 ,  H01L21/768

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a substrate and a transistor stack on the substrate. The transistor stack comprises a first transistor and a second transistor stacked in a first direction. The first transistor comprises first and second source/drain regions and a first channel region between the first and second source/drain regions, and the first source/drain region comprises a first metal layer. The second transistor comprises third and fourth source/drain regions and a second channel region between the third and fourth source/drain regions, and the first and third source/drain regions overlap each other in the first direction. The transistor stack further comprises a metal interconnector contacting the third source/drain region and the first metal layer of the first source/drain region material.

公开(公告)号：US11735585B2

公开(公告)日：2023-08-22

申请号：US17223829

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US11664433B2

公开(公告)日：2023-05-30

申请号：US17366534

申请日：2021-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Inchan Hwang

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/41775 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/0665

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate and may include a conductive contact. The upper transistor may include an upper source/drain region that overlaps a lower source/drain region of the lower transistor. The conductive contact may contact a side surface of the upper source/drain region and may overlap a center portion of the lower source/drain region. The side surface of the upper source/drain region may include a protrusion and a recess.

公开(公告)号：US12243946B2

公开(公告)日：2025-03-04

申请号：US17504755

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyoung Park ,  Seunghyun Song ,  Byounghak Hong ,  Seungchan Yun

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first channel layer including a first surface, a second channel layer that is spaced apart from the first channel layer in a first direction and includes a second surface, a first gate electrode and a second gate electrode. The first surface and the second surface may be spaced apart from each other in the first direction and may face opposite directions. The first channel layer may be in the first gate electrode, and the first gate electrode may be absent from the first surface of the first channel layer. The second channel layer may be in the second gate electrode, and the second gate electrode may be absent from the second surface of the second channel layer.

公开(公告)号：US12199152B2

公开(公告)日：2025-01-14

申请号：US17325083

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang-ill Seo ,  Daewon Ha ,  Jason Martineau

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/49

Abstract: Presented are structures and methods for forming such structures that allow for electrical or diffusion breaks between transistors of one level of a stacked transistor device, without necessarily requiring that a like electrical or diffusion break exists in another level of the stacked transistor device. Also presented, an electrical break between transistor devices may be formed by providing a channel of a first polarity with a false gate comprising a work-function metal of an opposite polarity.

公开(公告)号：US12051697B2

公开(公告)日：2024-07-30

申请号：US17361381

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song

IPC: H01L27/092 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/82385 ,  H01L25/074 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate, and the upper transistor may overlap the lower transistor. The upper transistor may include an upper gate structure, and the lower transistor may include a lower gate structure, and the upper gate structure and the lower gate structure may have different widths in a horizontal direction.