中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.022 seconds)

    Integrated circuit device
    23.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US11621256B2

    公开(公告)日：2023-04-04

    申请号：US17393934

    申请日：2021-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L23/00

    Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

    Integrated circuit device
    24.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US11411018B2

    公开(公告)日：2022-08-09

    申请号：US16923636

    申请日：2020-07-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

    IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11565

    Abstract: An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.

    Memory device
    25.
    发明授权
    Memory device 有权

    公开(公告)号：US11211391B2

    公开(公告)日：2021-12-28

    申请号：US16814491

    申请日：2020-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

    IPC: G11C16/04 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02

    Abstract: A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction. Each of the first and second cell contact regions includes first pads having different lengths to each other in the first direction and second pads different from the first pads, and the cell contacts are connected to the wordlines in the first pads. The number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region.

    Integrated circuit device
    26.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US11114428B2

    公开(公告)日：2021-09-07

    申请号：US16806030

    申请日：2020-03-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L23/00

    Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

    NONVOLATILE MEMORY DEVICE
    28.
    发明申请
    NONVOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20210118903A1

    公开(公告)日：2021-04-22

    申请号：US16878756

    申请日：2020-05-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwa Yun ,  Chanho Kim ,  Dongku Kang

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556

    Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

    MEMORY DEVICE
    29.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210091113A1

    公开(公告)日：2021-03-25

    申请号：US17023053

    申请日：2020-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  G11C8/14 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11526 ,  H01L23/528 ,  H01L27/11573

    Abstract: A memory device includes a peripheral circuit region comprising a first substrate, a plurality of metal layers over the first substrate, and a first metal pad, a cell region comprising a second substrate, a plurality of gate lines over the second substrate, a plurality of upper interconnection layers in the second substrate, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad, a common source line between the second substrate and the plurality of gate lines, the common source line comprising a through hole, and a word line cut region extending across the plurality of gate lines and extending through the through hole of the common source line to be connected to a first upper interconnection layer from among the plurality of upper interconnection layers.

Patent Agency Ranking