公开(公告)号：US20220231027A1

公开(公告)日：2022-07-21

申请号：US17716194

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Dongsoo Woo ,  Wonchul Lee

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

公开(公告)号：US11189618B2

公开(公告)日：2021-11-30

申请号：US15966554

申请日：2018-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namho Jeon ,  Jin-Seong Lee ,  Hyun-jung Lee ,  Dongsoo Woo ,  Donggyu Heo ,  Jaeho Hong

IPC: H01L27/105 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/108

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

公开(公告)号：US20210193664A1

公开(公告)日：2021-06-24

申请号：US16993394

申请日：2020-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Dongsoo Woo ,  Wonchul Lee

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

公开(公告)号：US10263084B2

公开(公告)日：2019-04-16

申请号：US15868620

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junsoo Kim ,  Moonyoung Jeong ,  Satoru Yamada ,  Dongsoo Woo ,  Jiyoung Kim

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/108 ,  H01L27/088

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20190027480A1

公开(公告)日：2019-01-24

申请号：US15920628

申请日：2018-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

IPC: H01L27/108

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

公开(公告)号：US09673276B2

公开(公告)日：2017-06-06

申请号：US15194066

申请日：2016-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junsoo Kim ,  Dongjin Lee ,  Dongsoo Woo ,  Jun-Bum Lee ,  Sang-Il Han

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L29/0653 ,  H01L27/088 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

公开(公告)号：US20230075559A1

公开(公告)日：2023-03-09

申请号：US17741219

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

公开(公告)号：US11171038B2

公开(公告)日：2021-11-09

申请号：US16744446

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namho Jeon ,  Joonyoung Choi ,  Jiyoung Kim ,  Junsoo Kim ,  Dongsoo Woo

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L27/108

Abstract: A fabrication method of an integrated circuit semiconductor device includes: forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate; after forming the low dielectric pattern, forming a flow layer to bury the low dielectric pattern on the substrate; forming an epitaxial layer on the flow layer; and forming a transistor in the substrate comprising the low dielectric pattern buried by the flow layer and in the epitaxial layer.

公开(公告)号：US10861854B2

公开(公告)日：2020-12-08

申请号：US16707019

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US10535659B2

公开(公告)日：2020-01-14

申请号：US16038052

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.