公开(公告)号：US10062841B2

公开(公告)日：2018-08-28

申请号：US15362906

申请日：2016-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-mok Park ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.

公开(公告)号：US09941333B2

公开(公告)日：2018-04-10

申请号：US15288233

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/082 ,  H01L27/24 ,  H01L29/12 ,  H01L45/00 ,  H01L27/102 ,  G11C13/00

CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/1026 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US09805444B2

公开(公告)日：2017-10-31

申请号：US14957970

申请日：2015-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-jae Lee ,  Gwan-hyeob Koh ,  Dae-shik Kim ,  Bo-young Seo

IPC: G09G5/36 ,  G06T1/60 ,  G06F12/00 ,  G11C5/02 ,  G11C11/16

CPC classification number: G06T1/60 ,  G06F12/00 ,  G06F12/0238 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/12 ,  G09G2360/18 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695

Abstract: Magnetic random access memory (MRAM)-based frame buffering apparatus are provided that may reduce a size and power consumption thereof by using a pixel self-refresh (PSR) method. The MRAM-based frame buffering apparatus includes a frame buffer memory including magnetic random access memory (MRAM). The frame buffer memory stores at least one piece of frame data. The MRAM-based frame buffering apparatus further includes a magnetic field sensor configured to detect an external magnetic field; and a frame buffer controller configured to control the storing of the at least one piece of frame data according to the intensity of the detected external magnetic field.