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    System and method for memory bad block mamagement
    21.
    发明授权
    System and method for memory bad block mamagement 有权

    公开(公告)号：US12236101B2

    公开(公告)日：2025-02-25

    申请号：US18352509

    申请日：2023-07-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunseok Kim

    IPC: G06F3/06 ,  G06F12/02

    Abstract: A memory system includes a memory module and a memory controller to control semiconductor memory devices in the memory module. Each of the semiconductor memory devices provides the memory controller with an address of at least a defective memory cell row unrepairable with a redundancy resource in a memory cell array as unrepairable address information. The memory controller allocates a portion of a normal cell regions of at least one of the semiconductor memory devices as a reserved region, and remaps first and second unrepairable addresses to first and second physical addresses of the reserved region in response to first and second host physical addresses from a host matching the first and second unrepairable addresses, respectively. The first physical address and the second physical address are consecutive.

    System on chip and electronic device including the same
    22.
    发明授权
    System on chip and electronic device including the same 有权

    公开(公告)号：US12181950B2

    公开(公告)日：2024-12-31

    申请号：US17943857

    申请日：2022-09-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungchul Jeon ,  Jae Min Kim ,  Hyunseok Kim ,  Junho Huh

    IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3296 ,  H03K17/687

    Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

    Memory controller adjusting power, memory system including same, and operating method for memory system
    23.
    发明授权
    Memory controller adjusting power, memory system including same, and operating method for memory system 有权

    公开(公告)号：US12086428B2

    公开(公告)日：2024-09-10

    申请号：US17839388

    申请日：2022-06-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunseok Kim ,  Jingyu Heo ,  Inhae Kang ,  Jaeyoul Oh

    IPC: G06F12/00 ,  G06F3/06 ,  G06F13/00

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

    Abstract: An operating method for a memory system including a host and a memory system. The operating method may include; communicating maximum power information from the memory system to the host, communicating power table information and battery information from the host to the memory system in response to the maximum power information, and controlling power consumption by a component of the memory system in response to a maximum consumption power value, wherein each of the power table information and the battery information is related to a battery associated with the memory system and operating in accordance with battery steps, the power table information includes a number of entries including a first entry and a second entry, the first entry is related to a first battery step among the battery steps and associated with a first maximum consumption power value, the second entry is related to a second battery step among the battery steps and associated with a second maximum consumption power value, and the maximum consumption power value controlling power consumption by the component of the memory system is one of the first maximum consumption power value and the second maximum consumption power value.

    SEMICONDUCTOR PACKAGE
    25.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230131531A1

    公开(公告)日：2023-04-27

    申请号：US17946461

    申请日：2022-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunseok Kim ,  Dahye Lee ,  Wanho Park

    IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

    Abstract: A semiconductor package includes: a package substrate, a first stack structure disposed on the package substrate, the first stack structure including first semiconductor chips stacked and connected to each other by bonding wires, a second stack structure disposed on the first stack structure, and including second semiconductor chips stacked, the second stack structure having an overhang region protruding beyond an uppermost first semiconductor chip of the first stack structure among the first semiconductor chips, an adhesive member covering a lower surface of the second stack structure and adhered to a portion of upper surfaces of the first stack structure, and an encapsulant disposed on the package substrate and covering the first stack structure and the second stack structure, wherein at least a portion of the bonding wires are buried in the die adhesive film in the overhang region to support the second stack structure.

    Storage device sharing attribute information with host device to use host memory buffer and electronic device including the same
    27.
    发明授权
    Storage device sharing attribute information with host device to use host memory buffer and electronic device including the same 有权

    公开(公告)号：US10936245B2

    公开(公告)日：2021-03-02

    申请号：US16012807

    申请日：2018-06-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jison Im ,  Hyunseok Kim ,  Hyun-Sik Yun ,  Hoju Jung

    IPC: G06F3/06 ,  G06F12/02

    Abstract: A storage device includes a memory device and a controller. The memory device stores attribute information associated with a host memory buffer allocated on a host memory. The controller communicates with the host memory such that a plurality of pieces of data associated with operations of the memory device is buffered, based on the attribute information, in a plurality of host memory buffers allocated on the host memory. The controller communicates with the host memory such that first data corresponding to a first attribute group managed in the attribute information is buffered in a first host memory buffer among the plurality of host memory buffers and second data corresponding to a second attribute group different from the first attribute group is buffered in a second host memory buffer separate from the first host memory buffer.

    SYSTEM ON CHIP AND ELECTRONIC DEVICE INCLUDING THE SAME
    29.
    发明申请
    SYSTEM ON CHIP AND ELECTRONIC DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230004210A1

    公开(公告)日：2023-01-05

    申请号：US17943857

    申请日：2022-09-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungchul JEON ,  Jae Min Kim ,  Hyunseok Kim ,  Junho Huh

    IPC: G06F1/3287 ,  G06F1/3296 ,  H03K17/687

    Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

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