公开(公告)号：US10852969B2

公开(公告)日：2020-12-01

申请号：US16363034

申请日：2019-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US12158809B2

公开(公告)日：2024-12-03

申请号：US18295457

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Young Lee ,  Sung-Joon Kim ,  Ilho Kim ,  Kyungjin Park ,  Changho Yun ,  Jinhun Jeong ,  Insu Choi ,  Kyung-Hee Han ,  Yukyoung Kim ,  Jinwoo Kim ,  Chaeeun Lee ,  Yunmi Hwang

IPC: G06F11/10 ,  G06F11/07

Abstract: Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

公开(公告)号：US20240168846A1

公开(公告)日：2024-05-23

申请号：US18328959

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhun JEONG ,  Sung-Joon Kim ,  Ilho Kim ,  Kyungjin Park ,  Changho Yun ,  Ho-Young Lee ,  Jongwon Jeong ,  Insu Choi ,  Kyung-Hee Han ,  Yunmi Hwang

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1438

Abstract: A method for preparing error recovery of a memory device included in a memory system includes performing a training operation of the memory device upon power-on of the memory system, booting an operating system into a normal mode by operating the memory device using a selected operation frequency of a plurality of operation frequencies based on results of the training operation, detecting an error frequency among the plurality of operation frequencies in response to a change of the selected operation frequency of the memory device by the operating system, the error frequency being an operation frequency which causes at least one error in the memory device, and storing information regarding the detected error frequency in a first register included in a memory controller associated with the memory device.

公开(公告)号：US11887692B2

公开(公告)日：2024-01-30

申请号：US17535861

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Insu Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1009 ,  G11C7/109 ,  G11C7/1063 ,  G11C8/18

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

公开(公告)号：US11670355B2

公开(公告)日：2023-06-06

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40618

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11360837B2

公开(公告)日：2022-06-14

申请号：US17198979

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoung Lee ,  Dongyoon Kim ,  Minhyouk Kim ,  Jihyuk Oh ,  Insu Choi

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F12/1036 ,  G06F9/455

Abstract: A method of operating a system running a virtual machine that executes an application and an operating system (OS) includes performing first address translation from first virtual addresses to first physical addresses, identifying faulty physical addresses among the first physical addresses, each faulty physical address corresponding to a corresponding first physical address associated with a faulty memory cell, analyzing a row address and a column address of each faulty physical address and specifying a fault type of the faulty physical addresses based on the analyzing of the row address and the column address of each faulty physical address, and performing second address translation from second virtual addresses to second physical addresses based on a faulty address, thereby excluding the faulty address from the second physical addresses.

公开(公告)号：US11321177B2

公开(公告)日：2022-05-03

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C11/4091 ,  G11C11/408

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US20200174882A1

公开(公告)日：2020-06-04

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/00 ,  G11C11/406

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.