公开(公告)号：US10460935B2

公开(公告)日：2019-10-29

申请号：US15817979

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Hyeonjin Shin ,  Jaeho Lee ,  Haeryong Kim

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/24 ,  H01L29/41 ,  H01L29/16

Abstract: An electronic device includes first and second electrodes that are spaced apart from each other and a 2D material layer. The 2D material layer connects the first and second electrodes. The 2D material layer includes a plurality of 2D nanomaterials. At least some of the 2D nanomaterials overlap one another.

公开(公告)号：US10229881B2

公开(公告)日：2019-03-12

申请号：US14814938

申请日：2015-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae Song ,  Seunggeol Nam ,  Yeonchoo Cho ,  Seongjun Park ,  Hyeonjin Shin ,  Jaeho Lee

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US10138543B2

公开(公告)日：2018-11-27

申请号：US14810948

申请日：2015-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjun Jeong ,  Jaeho Lee ,  Seongjun Park

IPC: C23C14/34 ,  C23C16/455 ,  C23C16/56 ,  C23C16/04 ,  C23C16/26 ,  C23C16/40 ,  C23C16/52 ,  G06T7/00

Abstract: A method of analyzing growth of a two-dimensional material includes forming a two-dimensional material layer includes defects on a substrate, depositing detection material layers on the defects, and one of (i) capturing an image of the two-dimensional material layer on which the detection material layers are deposited and processing the captured image, or (ii) obtaining map coordinates of the detection material layers and processing the obtained map coordinates.

公开(公告)号：US10134676B2

公开(公告)日：2018-11-20

申请号：US14932439

申请日：2015-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Lee ,  Taeho Kim ,  Seongjun Park

IPC: H01L23/532 ,  H01L23/498

Abstract: A flexible device includes an electronic device having an electrode and a flexible interconnect layer formed on the electrode. The flexible interconnect layer includes a two-dimensional (2D) material and a conductive polymer to have high electric conductivity and flexibility. The flexible device includes a flexible interconnect layer of one or more layers, and in this case, includes a low-dielectric constant dielectric layer between the respective layers.

公开(公告)号：US10074737B2

公开(公告)日：2018-09-11

申请号：US14932392

申请日：2015-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Lee ,  Kiyoung Lee ,  Sangyeob Lee ,  Eunkyu Lee ,  Jinseong Heo ,  Seongjun Park

IPC: H01L23/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/778 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/66477 ,  H01L29/78603 ,  H01L29/78684 ,  H01L51/0541

Abstract: A method of manufacturing a flexible device including a two-dimensional (2D) material, e.g., graphene, includes forming a dielectric layer on a first substrate, forming a two-dimensional (2D) material layer on the dielectric layer; forming a pattern in the 2D material layer, forming a second substrate on the dielectric layer and the 2D material layer, the first substrate including a flexible material, removing the first substrate, and forming a source electrode, a drain electrode, and a gate electrode on the dielectric layer.

公开(公告)号：US09660036B2

公开(公告)日：2017-05-23

申请号：US14928026

申请日：2015-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyowon Kim ,  Jaeho Lee

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  C01B31/04 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L29/1606 ,  C01B32/186 ,  C01B2204/02 ,  C01B2204/22 ,  C01B2204/30 ,  H01L21/02527 ,  H01L21/02573 ,  H01L21/02645 ,  H01L29/6603 ,  H01L51/0045 ,  H01L51/0558 ,  Y02E10/549

Abstract: A graphene layer, a method of forming the graphene layer, a device including the graphene layer, and a method of manufacturing the device are provided. The method of forming the graphene layer may include forming a first graphene at a first temperature using a first source gas and forming a second graphene at a second temperature using a second source gas. One of the first and second graphenes may be a P-type graphene, and the other one of the first and second graphenes may be an N-type graphene. The first graphene and the second graphene together form a P—N junction.

公开(公告)号：US09515144B2

公开(公告)日：2016-12-06

申请号：US14747243

申请日：2015-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Jaeho Lee ,  Jin-seong Heo ,  Kiyoung Lee

IPC: H01L29/16 ,  H01L29/786 ,  H01L29/423 ,  H01L29/778 ,  H01L29/06 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L29/1606 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/778 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Example embodiments relate to a fin-type graphene device. The fin-type graphene device includes a substrate, a graphene channel layer substantially vertical to the substrate, a gate insulating layer that covers one side surface of the graphene channel layer, a gate electrode on the gate insulating layer, and a source electrode and a drain electrode that are formed separately from each other on other side surface of the graphene channel layer.

Abstract translation: 示例性实施例涉及翅片型石墨烯装置。 翅片型石墨烯装置包括基板，基本上垂直于基板的石墨烯通道层，覆盖石墨烯通道层的一个侧表面的栅极绝缘层，栅极绝缘层上的栅电极以及源极和 漏电极，其在石墨烯通道层的另一侧表面上彼此分开形成。

公开(公告)号：US12191348B2

公开(公告)日：2025-01-07

申请号：US18462909

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Lee ,  Boeun Park ,  Younggeun Park ,  Jooho Lee

IPC: H01L23/66 ,  H01L49/02

Abstract: Provided are capacitors of semiconductor devices, wherein the capacitors may be used in a high-frequency operation environment. A capacitor includes a first electrode layer, a dielectric layer on the first electrode layer, and a second electrode layer on the dielectric layer, wherein the dielectric layer includes a plurality of unit dielectric layers, and the unit dielectric layer includes first and second sub-dielectric layers that have different dielectric constants and conductivities from each other and are connected in series, and the first and second sub-dielectric layers have a conductivity difference so that the capacitance of the dielectric layer converges to the capacitance of the unit dielectric layer.

公开(公告)号：US12068360B2

公开(公告)日：2024-08-20

申请号：US18175095

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggyu Song ,  Younsoo Kim ,  Jaeho Lee

IPC: H01L29/00 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/40 ,  H01L28/75 ,  H10B12/31

Abstract: A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al2O3 film between the top electrode and the dielectric film, wherein the doped Al2O3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al2O3.

公开(公告)号：US11868870B2

公开(公告)日：2024-01-09

申请号：US16556424

申请日：2019-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungho Kim ,  Cheheung Kim ,  Jaeho Lee

IPC: G06N3/063 ,  G06F7/523 ,  G06F7/501 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06F7/501 ,  G06F7/523 ,  G11C11/54

Abstract: A neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. The single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. The controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.