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    VARIABLE RESISTANCE MEMORY DEVICE
    21.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE 有权

    公开(公告)号：US20210202840A1

    公开(公告)日：2021-07-01

    申请号：US16999285

    申请日：2020-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

    CAPACITOR AND ELECTRONIC DEVICE INCLUDING THE SAME
    26.
    发明公开
    CAPACITOR AND ELECTRONIC DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240258366A1

    公开(公告)日：2024-08-01

    申请号：US18350397

    申请日：2023-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changsoo LEE ,  Jinhong KIM ,  Cheheung KIM ,  Jooho LEE ,  Yong-Hee CHO

    IPC: H10B12/00

    CPC classification number: H01L28/90 ,  H10B12/315

    Abstract: A capacitor is provided. The capacitor includes a first electrode, a second electrode disposed to face the first electrode, a dielectric layer of a rutile phase, disposed between the first electrode and the second electrode, and an interface layer between the first electrode and the dielectric layer, wherein the interface layer includes a first interface layer and a second interface layer, the first interface layer is adjacent to the first electrode, the second interface layer is adjacent to the dielectric layer, the first interface layer includes a conductive metal oxide having a work function in a range of about 4.8 eV to about 6.0 eV, the second interface layer includes a metal oxide having a rutile-phase crystal structure, and a thickness of the second interface layer is smaller than a thickness of the first interface layer.

    MEMORY DEVICE INCLUDING VERTICAL STACK STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    29.
    发明申请
    MEMORY DEVICE INCLUDING VERTICAL STACK STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220310827A1

    公开(公告)日：2022-09-29

    申请号：US17459527

    申请日：2021-08-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yumin KIM ,  Doyoon KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

    IPC: H01L29/68 ,  H01L27/115

    Abstract: Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.

    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    30.
    发明申请
    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220077235A1

    公开(公告)日：2022-03-10

    申请号：US17317154

    申请日：2021-05-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yumin KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

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