公开(公告)号：US20200251376A1

公开(公告)日：2020-08-06

申请号：US16854979

申请日：2020-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu Hee HAN ,  Jong Min BAEK ,  Viet Ha NGUYEN ,  Woo Kyung YOU ,  Sang Shin JANG ,  Byung Hee KIM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

公开(公告)号：US20190304903A1

公开(公告)日：2019-10-03

申请号：US16446226

申请日：2019-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Eui Bok LEE ,  Jong Min BAEK ,  Su Hyun BARK ,  Jang Ho LEE ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

公开(公告)号：US20190244896A1

公开(公告)日：2019-08-08

申请号：US16008319

申请日：2018-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Jong Min BAEK ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

Abstract: A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.

公开(公告)号：US20180102280A1

公开(公告)日：2018-04-12

申请号：US15636889

申请日：2017-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Viet Ha NGUYEN ,  Nae In LEE ,  Thomas OSZINDA ,  Byung Hee KIM ,  Jong Min BAEK ,  Tae Jin YIM

IPC: H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76888

Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.

公开(公告)号：US20180096880A1

公开(公告)日：2018-04-05

申请号：US15612102

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu Hee HAN ,  Jong Min BAEK ,  Viet Ha NGUYEN ,  Woo Kyung YOU ,  Sang Shin JANG ,  Byung Hee KIM

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

公开(公告)号：US20180053685A1

公开(公告)日：2018-02-22

申请号：US15802724

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Jong Min BAEK ,  Myung Geun SONG ,  Woo Kyung YOU ,  Byung Kwon CHO ,  Byung Hee KIM ,  Na Ein LEE

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.