公开(公告)号：US20200091349A1

公开(公告)日：2020-03-19

申请号：US16435657

申请日：2019-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dong Won KIM ,  Geum Jong BAE ,  Kwan Young CHUN

IPC: H01L29/786 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

公开(公告)号：US20220406779A1

公开(公告)日：2022-12-22

申请号：US17894427

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L29/16 ,  H01L21/8238

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20210320213A1

公开(公告)日：2021-10-14

申请号：US17354605

申请日：2021-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dong Won KIM ,  Geum Jong BAE ,  Kwan Young CHUN

IPC: H01L29/786 ,  H01L27/11 ,  H01L29/423 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

公开(公告)号：US20210091211A1

公开(公告)日：2021-03-25

申请号：US16857621

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dongwon KIM ,  Minyi KIM ,  Keun Hwi CHO

IPC: H01L29/732 ,  H01L21/8228 ,  H01L21/8238 ,  H01L29/735 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

公开(公告)号：US20210020638A1

公开(公告)日：2021-01-21

申请号：US17030841

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol SHIN ,  Myung Gil KANG ,  Sadaaki MASUOKA ,  Sang Hoon LEE ,  Sung Man WHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L29/16 ,  H01L21/8238

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

公开(公告)号：US20200243682A1

公开(公告)日：2020-07-30

申请号：US16845591

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Hee PARK ,  Myung Gil KANG ,  Young-Seok SONG ,  Keon Yong CHEON

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66

Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

公开(公告)号：US20170345897A1

公开(公告)日：2017-11-30

申请号：US15256136

申请日：2016-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Gil KANG ,  Seung Han PARK ,  Yong Hee PARK ,  Sang Hoon BAEK ,  Sang Woo LEE ,  Keon Yong CHEON ,  Sung Man WHANG

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/7827 ,  H01L29/7851

Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.