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公开(公告)号：US20230268385A1
公开(公告)日：2023-08-24
申请号：US18309407
申请日：2023-04-28
发明人： Sanghyun Jo , Eunha Lee , Jinseong Heo , Junghwa Kim , Hyangsook Lee , Seunggeol Nam
IPC分类号： H01L29/06 , H01L23/29 , H01L29/423 , H01L29/66
CPC分类号： H01L29/0649 , H01L23/291 , H01L29/4236 , H01L29/66977
摘要： An electronic device includes a dielectric layer including crystal grains having aligned crystal orientations the dielectric layer may be between a substrate and a gate electrode. The dielectric layer may be between isolated first and second electrodes. A method of manufacturing an electronic device may include preparing a substrate having a channel layer, forming the dielectric layer on the channel layer, and forming a gate electrode on the dielectric layer.
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公开(公告)号：US11646375B2
公开(公告)日：2023-05-09
申请号：US17112355
申请日：2020-12-04
发明人： Yunseong Lee , Jinseong Heo , Sangwook Kim , Taehwan Moon , Sanghyun Jo
IPC分类号： H01L29/78 , H01L27/1159 , H01L29/51 , H01L21/02
CPC分类号： H01L29/78391 , H01L29/516 , H10B51/30 , H01L21/02181 , H01L21/02189
摘要： Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.
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公开(公告)号：US11522082B2
公开(公告)日：2022-12-06
申请号：US17001979
申请日：2020-08-25
发明人： Jinseong Heo , Sangwook Kim , Yunseong Lee , Sanghyun Jo , Hyangsook Lee
摘要： Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.
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公开(公告)号：US11349026B2
公开(公告)日：2022-05-31
申请号：US16682380
申请日：2019-11-13
发明人： Yunseong Lee , Jinseong Heo , Sangwook Kim , Sanghyun Jo
IPC分类号： H01L29/78 , H01L29/51 , H01L29/423 , H01L21/02 , H01L29/66 , H01L29/08 , H01L27/1159
摘要： An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.
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公开(公告)号：US11145731B2
公开(公告)日：2021-10-12
申请号：US16923514
申请日：2020-07-08
发明人： Taehwan Moon , Eunha Lee , Junghwa Kim , Hyangsook Lee , Sanghyun Jo , Jinseong Heo
IPC分类号： H01L21/02 , H01L29/423 , H01L21/28 , H01L27/108 , H01L49/02 , H01L29/51
摘要： Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.
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公开(公告)号：US11024748B2
公开(公告)日：2021-06-01
申请号：US15892850
申请日：2018-02-09
发明人： Jaeho Lee , Haeryong Kim , Sanghyun Jo , Hyeonjin Shin
IPC分类号： H01L29/788 , H01L29/423 , H01L29/49 , H01L27/11521 , G11C11/54 , G11C11/56 , H01L29/786 , H01L29/06 , G11C13/02 , H01L21/28 , G11C16/04 , G11C16/26 , G11C16/10 , B82Y10/00
摘要： Provided are nonvolatile memory devices including 2-dimensional (2D) material and apparatuses including the nonvolatile memory devices. A nonvolatile memory device may include a storage stack including a plurality of charge storage layers between a channel element and a gate electrode facing the channel element. The plurality of charge storage layers may include a 2D material. An interlayer barrier layer may be further provided between the plurality of charge storage layers. The nonvolatile memory device may have a multi-bit or multi-level memory characteristic due to the plurality of charge storage layers.
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公开(公告)号：US10714500B2
公开(公告)日：2020-07-14
申请号：US16244243
申请日：2019-01-10
发明人： Jinseong Heo , Yunseong Lee , Sanghyun Jo
摘要： Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.
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公开(公告)号：US20200091306A1
公开(公告)日：2020-03-19
申请号：US16259038
申请日：2019-01-28
发明人： Jinseong Heo , Yunseong Lee , Sanghyun Jo , Keunwook Shin , Hyeonjin Shin
摘要： Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.
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公开(公告)号：US12094971B2
公开(公告)日：2024-09-17
申请号：US18310022
申请日：2023-05-01
发明人： Yunseong Lee , Jinseong Heo , Sangwook Kim , Sanghyun Jo
IPC分类号： H01L29/78 , H01L21/02 , H01L21/28 , H01L29/08 , H01L29/423 , H01L29/51 , H01L29/66 , H10B51/30
CPC分类号： H01L29/78391 , H01L21/02175 , H01L21/022 , H01L21/0228 , H01L29/0847 , H01L29/40111 , H01L29/42364 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/6684 , H01L21/02181 , H01L21/02189 , H10B51/30
摘要： An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.
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公开(公告)号：US11862705B2
公开(公告)日：2024-01-02
申请号：US17208018
申请日：2021-03-22
发明人： Jinseong Heo , Yunseong Lee , Taehwan Moon , Sanghyun Jo
CPC分类号： H01L29/516 , H01L21/28158 , H01L29/40111
摘要： An electronic device includes a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer. The ferroelectric layer is configured to be aligned in a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer.
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