公开(公告)号：US12205951B2

公开(公告)日：2025-01-21

申请号：US17491841

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook Kim ,  Seunggeol Nam ,  Taehwan Moon ,  Kwanghee Lee ,  Jinseong Heo ,  Hagyoul Bae ,  Yunseong Lee

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

公开(公告)号：US12044961B2

公开(公告)日：2024-07-23

申请号：US17188140

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pilsoo Kang ,  Wonchan Lee ,  Sangwook Kim ,  Sungyong Moon ,  Seunghune Yang ,  Jeeeun Jung

IPC: G03F1/70 ,  G03F1/24 ,  G03F1/36 ,  H01L21/033

CPC classification number: G03F1/70 ,  G03F1/24 ,  H01L21/0334 ,  G03F1/36

Abstract: A mask forming method includes providing preliminary mask data including a Manhattan path such as a quadrangle, a bar, a polygon or a combination thereof based on a layout. Mask data including a curvilinear shape is prepared by correcting the preliminary mask data through application of an elliptical function, a B-spline curve, or a combination thereof. A mask pattern is formed on a mask substrate based on the mask data.

公开(公告)号：US11604971B2

公开(公告)日：2023-03-14

申请号：US16414257

申请日：2019-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaechul Park ,  Sangwook Kim

IPC: G06N3/063 ,  H01L25/065 ,  G11C13/00

Abstract: A neuromorphic apparatus includes a three-dimensionally-stacked synaptic structure, and includes a plurality of unit synaptic modules, each of the plurality of unit synaptic modules including a plurality of synaptic layers, each of the plurality of synaptic layers including a plurality of stacked layers, and each of the plurality of unit synaptic modules further including a first decoder interposed between two among the plurality of synaptic layers. The neuromorphic apparatus further includes a second decoder that provides a level selection signal to the first decoder included in one among the plurality of unit synaptic modules to be accessed, and a third decoder that generates an address of one among a plurality of memristers to be accessed in a memrister array of one among the plurality of synaptic layers included in the one among the plurality of unit synaptic modules to be accessed.

公开(公告)号：US11556160B2

公开(公告)日：2023-01-17

申请号：US16769302

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kunsuk Kim ,  Jehwan Lee ,  Sangwook Kim

IPC: G06F1/28 ,  G06F1/20 ,  H02M3/158

Abstract: Disclosed in various embodiments of the present invention are an electronic device for adjusting a voltage and an operating method therefor. The electronic device comprises: at least one first converter for supporting a plurality of operating modes for changing voltage; a second converter supporting the plurality of operating modes and connected with the at least one first converter in series; and at least one processor, wherein the processor can be configured to determine an intermediate voltage between the at least one first converter and the second converter on the basis of an input voltage of the at least one first converter and an output voltage of the second converter, and control an operating mode of each of the at least one first converter and the second converter on the basis of the determined intermediate voltage. Other embodiments are also possible.

公开(公告)号：US11527646B2

公开(公告)日：2022-12-13

申请号：US17026665

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Sangwook Kim ,  Yunseong Lee ,  Sanghyun Jo

IPC: H01L29/78 ,  H01L21/28 ,  G11C11/22 ,  H01L29/66

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

公开(公告)号：US11417763B2

公开(公告)日：2022-08-16

申请号：US16682512

申请日：2019-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook Kim ,  Yunseong Lee ,  Sanghyun Jo ,  Jinseong Heo

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/66

Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.

公开(公告)号：US12170336B2

公开(公告)日：2024-12-17

申请号：US17540607

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee Lee ,  Sangwook Kim

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

公开(公告)号：US11989646B2

公开(公告)日：2024-05-21

申请号：US18166859

申请日：2023-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaechul Park ,  Sangwook Kim

IPC: G06N3/063 ,  G11C13/00 ,  H01L25/065

CPC classification number: G06N3/063 ,  G11C13/0023 ,  G11C13/003 ,  H01L25/0657

Abstract: A neuromorphic apparatus includes a three-dimensionally-stacked synaptic structure, and includes a plurality of unit synaptic modules, each of the plurality of unit synaptic modules including a plurality of synaptic layers, each of the plurality of synaptic layers including a plurality of stacked layers, and each of the plurality of unit synaptic modules further including a first decoder interposed between two among the plurality of synaptic layers. The neuromorphic apparatus further includes a second decoder that provides a level selection signal to the first decoder included in one among the plurality of unit synaptic modules to be accessed, and a third decoder that generates an address of one among a plurality of memristers to be accessed in a memrister array of one among the plurality of synaptic layers included in the one among the plurality of unit synaptic modules to be accessed.

公开(公告)号：US11824117B2

公开(公告)日：2023-11-21

申请号：US17308543

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee Lee ,  Sangwook Kim ,  Jinseong Heo

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H01L29/6684

Abstract: An oxide semiconductor transistor includes: an insulating substrate including a trench; a gate electrode in the trench; an oxide semiconductor layer on a surface of the insulating substrate, the surface exposed through the trench; and a ferroelectric layer between the gate electrode and the oxide semiconductor layer, wherein the oxide semiconductor layer may include a source region and a drain region which are on the insulating substrate outside the trench and are apart from each other with the gate electrode therebetween.

公开(公告)号：US11646375B2

公开(公告)日：2023-05-09

申请号：US17112355

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong Lee ,  Jinseong Heo ,  Sangwook Kim ,  Taehwan Moon ,  Sanghyun Jo

IPC: H01L29/78 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H10B51/30 ,  H01L21/02181 ,  H01L21/02189

Abstract: Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.