公开(公告)号：US11424264B2

公开(公告)日：2022-08-23

申请号：US16838586

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US11387253B2

公开(公告)日：2022-07-12

申请号：US16910199

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Junghwan Kim ,  Chanhyoung Kim

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10

Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extended area of the vertical structure.

公开(公告)号：US20210098480A1

公开(公告)日：2021-04-01

申请号：US16903026

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  G11C5/06

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.

公开(公告)号：US10930739B2

公开(公告)日：2021-02-23

申请号：US16186915

申请日：2018-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Dongkyum Kim ,  Sunggil Kim ,  Seulye Kim ,  Sangsoo Lee ,  Hyeeun Hong

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.

公开(公告)号：US20190206886A1

公开(公告)日：2019-07-04

申请号：US16298247

申请日：2019-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L29/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/08

CPC classification number: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

公开(公告)号：US10090323B2

公开(公告)日：2018-10-02

申请号：US15484339

申请日：2017-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon Choi ,  Sung Gil Kim ,  Seulye Kim ,  Jung Ho Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jae Young Ahn ,  Han Jin Lim

IPC: H01L29/792 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.