公开(公告)号：US20230013611A1

公开(公告)日：2023-01-19

申请号：US17954532

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan Ro ,  Shinhaeng Kang ,  Seongwook Park ,  Seungwoo Seo

IPC: G06F3/06 ,  G06F7/523 ,  G06N3/063

Abstract: A memory device includes: memory operation circuitries to perform memory processing; memory banks assigned to one of the memory operation circuitries such that a set of n memory banks is assigned to each of the memory operation circuitries; and command pads to receive a command signal from an external source, wherein, for each of the memory operation circuitries, a corresponding memory operation circuitry to access memory banks of a corresponding set of n memory banks that is assigned to the corresponding memory operation circuitry, in an order determined based on respective distances from each of the memory banks of the corresponding set of n memory banks to the command pads, and wherein, each of the memory banks of the corresponding set of n memory banks to perform an access operation of data requested by the corresponding memory operation circuitry while the memory processing is performed.

公开(公告)号：US20200293319A1

公开(公告)日：2020-09-17

申请号：US16814462

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

IPC: G06F9/30 ,  G06F9/32

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

公开(公告)号：US20250094092A1

公开(公告)日：2025-03-20

申请号：US18970303

申请日：2024-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan Ro ,  Shinhaeng Kang ,  Seongwook Park ,  Seungwoo Seo

IPC: G06F3/06 ,  G06F7/523 ,  G06N3/063

Abstract: A memory device includes: memory operation circuitries to perform memory processing; memory banks assigned to one of the memory operation circuitries such that a set of n memory banks is assigned to each of the memory operation circuitries; and command pads to receive a command signal from an external source, wherein, for each of the memory operation circuitries, a corresponding memory operation circuitry to access memory banks of a corresponding set of n memory banks that is assigned to the corresponding memory operation circuitry, in an order determined based on respective distances from each of the memory banks of the corresponding set of n memory banks to the command pads, and wherein, each of the memory banks of the corresponding set of n memory banks to perform an access operation of data requested by the corresponding memory operation circuitry while the memory processing is performed.

公开(公告)号：US12079482B2

公开(公告)日：2024-09-03

申请号：US17934691

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Sukhan Lee ,  Kyomin Sohn

IPC: G11C7/10 ,  G06F3/06 ,  G11C8/00

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0673 ,  G11C7/1006 ,  G11C8/00

Abstract: A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.

公开(公告)号：US12073191B2

公开(公告)日：2024-08-27

申请号：US17965351

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Sukhan Lee

IPC: G06F7/487 ,  G06F5/01 ,  G06F7/544 ,  G06F9/30

CPC classification number: G06F7/4876 ,  G06F5/012 ,  G06F7/5443 ,  G06F9/3001

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

公开(公告)号：US20240256452A1

公开(公告)日：2024-08-01

申请号：US18339488

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Suk Han Lee ,  Kyomin Sohn

IPC: G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: Disclosed is a semiconductor memory device and a memory system, including at least one high-bandwidth memory device configured to store data or output stored data according to an access command, a processor configured to generate the access command for the high-bandwidth memory device, and a logic die on the high-bandwidth memory device and including a last level cache providing a cache function to the processor. The last level cache is configured to perform a cache bypassing operation to directly access the high-bandwidth memory device without a cache replacement operation when an invalid line and a clean line do not exist in a cache miss state in response to a cache read or cache write request by the processor.

公开(公告)号：US12026611B2

公开(公告)日：2024-07-02

申请号：US16426744

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsun Park ,  Junhaeng Lee ,  Shinhaeng Kang

IPC: G06N3/08 ,  G06N5/04

CPC classification number: G06N3/08 ,  G06N5/04

Abstract: A method of quantizing parameters of a neural network includes calculating, for each of the parameters, a bit shift value indicating a degree outside a bit range of a fixed-point format for quantizing the parameters, updating the fixed-point format based on the calculated bit shift values of the parameters, and quantizing parameters updated in a learning or inference process according to the updated fixed-point format.

公开(公告)号：US11386975B2

公开(公告)日：2022-07-12

申请号：US16456094

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Joonho Song ,  Seungwon Lee

IPC: G06F11/20 ,  G06F12/0815 ,  G11C29/38 ,  H01L25/065 ,  H01L25/18 ,  G11C29/00 ,  G01R31/3193

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

公开(公告)号：US20210397376A1

公开(公告)日：2021-12-23

申请号：US17098959

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan Ro ,  Shinhaeng Kang ,  Seongwook Park ,  Seungwoo Seo

IPC: G06F3/06 ,  G06N3/063 ,  G06F7/523

Abstract: A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.