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公开(公告)号：US11462255B2
公开(公告)日：2022-10-04
申请号：US17239854
申请日：2021-04-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngcheon Kwon , Jaeyoun Youn , Namsung Kim , Kyomin Sohn , Seongil O , Sukhan Lee
IPC: G11C11/406 , G11C11/4076 , G11C11/408 , G11C7/10
Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.
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公开(公告)号：US11416178B2
公开(公告)日：2022-08-16
申请号：US17014667
申请日：2020-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunsung Shin , Sanghyuk Kwon , Youngcheon Kwon , Sukhan Lee , Haesuk Lee
Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.
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公开(公告)号：US11094371B2
公开(公告)日：2021-08-17
申请号：US16810344
申请日：2020-03-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seongil O , Shinhaeng Kang , Namsung Kim , Kyomin Sohn , Sukhan Lee
IPC: G11C11/409 , G11C11/4096 , G06N3/063 , G06N3/04 , G06F13/16
Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.
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公开(公告)号：US20230214124A1
公开(公告)日：2023-07-06
申请号：US17934691
申请日：2022-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng Kang , Sukhan Lee , Kyomin Sohn
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0629 , G06F3/0673
Abstract: A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.
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公开(公告)号：US20230128183A1
公开(公告)日：2023-04-27
申请号：US17938789
申请日：2022-10-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Shinhaeng Kang , Sukhan Lee , Hweesoo Kim , Kyomin Sohn
IPC: G06F3/06
Abstract: A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.
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Patent Agency Ranking
公开(公告)号：US20220405165A1
公开(公告)日：2022-12-22
申请号：US17535762
申请日：2021-11-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yeonggeol Song , Sungrae Kim , Kijun Lee , Sunggi Ahn , Yesin Ryu , Sukhan Lee
Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.
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公开(公告)号：US11513770B2
公开(公告)日：2022-11-29
申请号：US16909214
申请日：2020-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng Kang , Sukhan Lee
Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.
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公开(公告)号：US12266414B2
公开(公告)日：2025-04-01
申请号：US18059124
申请日：2022-11-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaewon Park , Sukhan Lee
Abstract: Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.
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公开(公告)号：US12087388B2
公开(公告)日：2024-09-10
申请号：US17504918
申请日：2021-10-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hak-Soo Yu , Namsung Kim , Kyomin Sohn , Seongil O , Sukhan Lee
IPC: G11C7/10 , G11C5/02 , G11C11/408 , G11C11/409
CPC classification number: G11C7/1045 , G11C5/025 , G11C7/1039 , G11C11/4087 , G11C11/409
Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.
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公开(公告)号：US12079482B2
公开(公告)日：2024-09-03
申请号：US17934691
申请日：2022-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng Kang , Sukhan Lee , Kyomin Sohn
CPC classification number: G06F3/0613 , G06F3/0629 , G06F3/0673 , G11C7/1006 , G11C8/00
Abstract: A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.
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