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公开(公告)号：US11651800B2
公开(公告)日：2023-05-16
申请号：US17354613
申请日：2021-06-22
发明人： Feng Lu , Jongyeon Kim , Ohwon Kwon
CPC分类号： G11C7/065 , G11C7/106 , G11C7/1048 , G11C7/1063 , G11C7/1087
摘要： A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.
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公开(公告)号：US20230120352A1
公开(公告)日：2023-04-20
申请号：US17505179
申请日：2021-10-19
发明人： Yu-Chung Lien , Jiahui Yuan , Ohwon Kwon
IPC分类号： G11C16/34 , H01L27/11556 , H01L27/11582 , H01L25/065 , H01L25/18 , H01L23/00 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/26
摘要： A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.
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公开(公告)号：US11222694B1
公开(公告)日：2022-01-11
申请号：US16985837
申请日：2020-08-05
发明人： Sirisha Bhamidipati , Arka Ganguly , Ohwon Kwon , Chia-Kai Chou , Kou Tei
IPC分类号： G11C11/56 , G11C11/4091 , G11C16/08 , H01L27/11 , G11C16/24 , G11C11/4074
摘要： A storage device is disclosed herein. The storage device, comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and a reference current generator circuit configured to receive an input voltage from a voltage supply and generate therefrom a plurality of outputs, each output of the plurality of outputs used to generate one or more bias voltages/currents for one or more control signals. The control circuitry is configured to: receive a refresh read operation command; and adapt operation of the reference current generator circuit based on receiving the refresh read operation command. This proposal is also applicable for other test modes, such as SA stress, soft and preprogram, and SA test modes.
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公开(公告)号：US11139022B1
公开(公告)日：2021-10-05
申请号：US16908467
申请日：2020-06-22
发明人： Kou Tei , Ohwon Kwon , Jongyeon Kim , Chia-Kai Chou , Yuedan Li
IPC分类号： G11C7/02 , G11C11/4091 , G11C11/4074 , G11C5/02 , G11C11/4096 , G11C11/4076
摘要： An example of an apparatus includes a plurality of memory cells arranged in a plurality of NAND strings that are connected to a source line and a control circuit connected to the source line. The control circuit is configured to provide a first current to the source line to pre-charge the source line to a target voltage for sensing data states of the plurality of memory cells and provide a second current to the source line to return the source line to the target voltage in a recovery period between sensing data states. The control circuit is configured to provide the second current at any one of a plurality of current levels.
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公开(公告)号：US11139018B1
公开(公告)日：2021-10-05
申请号：US17007442
申请日：2020-08-31
发明人： Abu Naser Zainuddin , Ohwon Kwon , Jiahui Yuan
IPC分类号： G11C7/12 , G11C11/4074 , G11C11/4091 , G11C5/14 , G11C11/4097 , G11C11/4094 , G11C16/26 , G11C16/04 , G11C16/34 , G11C16/24 , G11C11/56
摘要： Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are controlled to reduce the channel resistance. Vcelsrc can be temporarily reduced, e.g., provided with a negative voltage kick, while Vp-well is non-decreasing during a read operation. The negative voltage kick decreases a body bias of the NAND string in its channel to reduce the channel resistance and increase the current. The negative voltage kick can be initiated when a bit line clamp transistor is made conductive to allow a current to flow in the NAND string. The magnitude and duration of the negative voltage kick can be adjusted based on various factors.
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公开(公告)号：US10971209B1
公开(公告)日：2021-04-06
申请号：US16593576
申请日：2019-10-04
发明人： Ohwon Kwon , Kou Tei , VSNK Chaitanya G
IPC分类号： G11C11/4074 , G11C5/14 , G11C11/56 , G11C11/4091 , G11C11/4094
摘要： A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.
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公开(公告)号：US10255978B2
公开(公告)日：2019-04-09
申请号：US15589120
申请日：2017-05-08
发明人： Kenneth Louie , Qui Nguyen , Tai-yuan Tseng , Jong Yuh , Ohwon Kwon
摘要： This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.
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公开(公告)号：US20170169867A1
公开(公告)日：2017-06-15
申请号：US15151617
申请日：2016-05-11
发明人： Amul DESAI , Hao Nguyen , Man Mui , Ohwon Kwon
CPC分类号： G11C7/12 , G05F1/463 , G11C7/04 , G11C7/08 , G11C7/10 , G11C7/1048 , G11C7/106 , G11C7/22 , H01L27/0211
摘要： The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.
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