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公开(公告)号：US20220406342A1
公开(公告)日：2022-12-22
申请号：US17354613
申请日：2021-06-22
发明人： Feng Lu , Jongyeon Kim , Ohwon Kwon
摘要： A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.
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公开(公告)号：US20180322928A1
公开(公告)日：2018-11-08
申请号：US15589120
申请日：2017-05-08
发明人： Kenneth Louie , Qui Nguyen , Tai-yuan Tseng , Jong Yuh , Ohwon Kwon
摘要： This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.
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公开(公告)号：US20230131500A1
公开(公告)日：2023-04-27
申请号：US17509725
申请日：2021-10-25
发明人： Xiang Yang , Arka Ganguly , Ohwon Kwon
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4074 , G06F3/06
摘要： An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.
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公开(公告)号：US10984877B1
公开(公告)日：2021-04-20
申请号：US16717233
申请日：2019-12-17
发明人： Jongyeon Kim , Hiroki Yabe , Kou Tei , Chia-Kai Chou , Ohwon Kwon
摘要： An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.
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公开(公告)号：US20240215240A1
公开(公告)日：2024-06-27
申请号：US18358584
申请日：2023-07-25
发明人： Ohwon Kwon , Yuki Mizutani , Arka Ganguly , Kou Tei , Yonggang Wu
摘要： Technology is disclosed herein for a memory device having a narrow gap between planes and a method of shrinking the gap between planes. A first and second adjacent planes each has a word line (WL) hookup region at mid-plane. A dummy array region resides between the two planes. The dummy array region may contain a stack of alternating layers of a first insulating material and a second insulating material. There is a first electrical isolation structure between the dummy array region and a stack in the first plane. There is a second electrical isolation structure between the dummy array region and a stack in a second plane. The electrical isolation structures may be formed in narrow trenches. The combination of the dummy array region and the two electrical isolation structures results in a very short gap between the adjacent planes.
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公开(公告)号：US11978516B2
公开(公告)日：2024-05-07
申请号：US17718124
申请日：2022-04-11
发明人： Yanjie Wang , Ohwon Kwon , Kou Tei , Tai-Yuan Tseng , Yasue Yamamoto , Yonggang Wu , Guirong Liang
IPC分类号： G11C16/04 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/34 , H01L23/00 , H01L25/065
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/30 , G11C16/3459 , H01L24/08 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L2224/08148 , H01L2224/16225 , H01L2224/48149 , H01L2224/48229 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06562
摘要： A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.
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公开(公告)号：US11935585B2
公开(公告)日：2024-03-19
申请号：US17509725
申请日：2021-10-25
发明人： Xiang Yang , Arka Ganguly , Ohwon Kwon
IPC分类号： G11C11/4096 , G06F3/06 , G11C11/4074 , G11C11/408
CPC分类号： G11C11/4096 , G06F3/0613 , G06F3/064 , G06F3/0659 , G06F3/0679 , G11C11/4074 , G11C11/4085
摘要： An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.
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公开(公告)号：US20230282288A1
公开(公告)日：2023-09-07
申请号：US17685613
申请日：2022-03-03
发明人： Xiang Yang , Deepanshu Dutta , Ohwon Kwon , James Kai , Yuki Mizutani
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/24
摘要： The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line. During some read operations, this allows the memory device to operate with lower power requirements.
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公开(公告)号：US20230187014A1
公开(公告)日：2023-06-15
申请号：US17550352
申请日：2021-12-14
发明人： Iris Lu , Yan Li , Ohwon Kwon
摘要： Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.
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公开(公告)号：US09959915B2
公开(公告)日：2018-05-01
申请号：US15151617
申请日：2016-05-11
发明人： Amul Desai , Hao Nguyen , Man Mui , Ohwon Kwon
CPC分类号： G11C7/12 , G05F1/463 , G11C7/04 , G11C7/08 , G11C7/10 , G11C7/1048 , G11C7/106 , G11C7/22 , H01L27/0211
摘要： The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.
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