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公开(公告)号：US20180322928A1
公开(公告)日：2018-11-08
申请号：US15589120
申请日：2017-05-08
发明人： Kenneth Louie , Qui Nguyen , Tai-yuan Tseng , Jong Yuh , Ohwon Kwon
摘要： This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.
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公开(公告)号：US20180197586A1
公开(公告)日：2018-07-12
申请号：US15625848
申请日：2017-06-16
发明人： Qui Nguyen , Alexander Chu , Kenneth Louie , Anirudh Amarnath , Jixin Yu , Yen-Lung Jason Li , Tai-Yuan Tseng , Jong Yuh
IPC分类号： G11C8/08 , G11C5/06 , H01L27/112 , G11C8/10 , G06F13/40
CPC分类号： G11C8/08 , G06F13/4072 , G11C5/06 , G11C8/10 , G11C8/14 , G11C16/08 , H01L27/112 , H01L27/11575 , H01L27/11582
摘要： Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.
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公开(公告)号：US10115440B2
公开(公告)日：2018-10-30
申请号：US15625848
申请日：2017-06-16
发明人： Qui Nguyen , Alexander Chu , Kenneth Louie , Anirudh Amarnath , Jixin Yu , Yen-Lung Jason Li , Tai-Yuan Tseng , Jong Yuh
IPC分类号： G11C8/08 , G11C5/06 , H01L27/112 , G11C8/10 , G06F13/40
摘要： Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.
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公开(公告)号：US09779832B1
公开(公告)日：2017-10-03
申请号：US15371462
申请日：2016-12-07
发明人： Muhammad Masuduzzaman , Deepanshu Dutta , Jong Yuh
CPC分类号： G11C16/3459 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/3495
摘要： In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.
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公开(公告)号：US10255978B2
公开(公告)日：2019-04-09
申请号：US15589120
申请日：2017-05-08
发明人： Kenneth Louie , Qui Nguyen , Tai-yuan Tseng , Jong Yuh , Ohwon Kwon
摘要： This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.
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公开(公告)号：US10217520B2
公开(公告)日：2019-02-26
申请号：US15685309
申请日：2017-08-24
发明人： Muhammad Masuduzzaman , Deepanshu Dutta , Jong Yuh
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04 , G11C16/26 , G11C16/08 , G11C16/24 , G11C16/30 , G11C11/56 , G11C16/16 , G11C7/10 , G11C7/22
摘要： In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.
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公开(公告)号：US20180158531A1
公开(公告)日：2018-06-07
申请号：US15685309
申请日：2017-08-24
发明人： Muhammad Masuduzzaman , Deepanshu Dutta , Jong Yuh
CPC分类号： G11C16/3459 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/3495
摘要： In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.
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