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    Memory system with error correction decoder architecture having reduced latency and increased throughput
    21.
    发明授权
    Memory system with error correction decoder architecture having reduced latency and increased throughput 有权
    具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量

    公开(公告)号：US08479085B2

    公开(公告)日：2013-07-02

    申请号：US12191458

    申请日：2008-08-14

    申请人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    发明人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

    摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

    摘要翻译： 存储器系统包括：包括纠错解码器的存储器控​​制器。 纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器 以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。 当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

    Memory devices and methods for determining data of bit layers based on detected error bits
    23.
    发明授权
    Memory devices and methods for determining data of bit layers based on detected error bits 有权
    用于基于检测到的错误位来确定位层的数据的存储器件和方法

    公开(公告)号：US07903459B2

    公开(公告)日：2011-03-08

    申请号：US12232150

    申请日：2008-09-11

    申请人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

    发明人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5621

    摘要： Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.

    摘要翻译： 公开了一种存储器件和存储器数据读取方法。 存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔， 单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。 在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压 检测到错误位。

    Memory programming method
    24.
    发明授权
    Memory programming method 有权
    内存编程方法

    公开(公告)号：US07885108B2

    公开(公告)日：2011-02-08

    申请号：US12382176

    申请日：2009-03-10

    申请人： Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong

    发明人： Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong

    IPC分类号： G11C16/00

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3418

    摘要： A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage.

    摘要翻译： 存储器编程方法可以包括基于要在所述多个存储器单元中的至少一个存储器单元中编程的数据的模式来改变要改变的阈值电压的多个存储器单元中的至少一个，将程序条件电压施加到 所述至少一个所识别的存储器单元，直到所述至少一个所识别的存储单元的阈值电压被包括在第一阈值电压间隔内，从而调整所述至少一个识别的存储单元的阈值电压，并且对所述存储单元中的数据进行编程 具有调整的阈值电压的至少一个识别的存储器单元。

    Memory programming method
    25.
    发明申请
    Memory programming method 有权
    内存编程方法

    公开(公告)号：US20090285022A1

    公开(公告)日：2009-11-19

    申请号：US12382176

    申请日：2009-03-10

    申请人： Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong

    发明人： Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong

    IPC分类号： G11C16/02 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3418

    摘要： A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage.

    摘要翻译： 存储器编程方法可以包括基于要在所述多个存储器单元中的至少一个存储器单元中编程的数据的模式来改变要改变的阈值电压的多个存储器单元中的至少一个，将程序条件电压施加到 所述至少一个所识别的存储器单元，直到所述至少一个所识别的存储单元的阈值电压被包括在第一阈值电压间隔内，从而调整所述至少一个识别的存储单元的阈值电压，并且对所述存储单元中的数据进行编程 具有调整的阈值电压的至少一个识别的存储器单元。

    Nonvolatile memory devices that utilize error correction estimates to increase reliability of error detection and correction operations
    26.
    发明授权
    Nonvolatile memory devices that utilize error correction estimates to increase reliability of error detection and correction operations 有权
    利用误差校正估计的非易失性存储器件增加错误检测和校正操作的可靠性

    公开(公告)号：US08239747B2

    公开(公告)日：2012-08-07

    申请号：US12216744

    申请日：2008-07-10

    申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

    发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

    摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

    摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

    Device for reading memory data and method using the same
    28.
    发明授权
    Device for reading memory data and method using the same 有权
    用于读取存储器数据的装置和使用其的方法

    公开(公告)号：US07751239B2

    公开(公告)日：2010-07-06

    申请号：US11907082

    申请日：2007-10-09

    申请人： Kyoung Lae Cho ,  Jun Jin Kong ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Sung-Jae Byun ,  Dong Ku Kang

    发明人： Kyoung Lae Cho ,  Jun Jin Kong ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Sung-Jae Byun ,  Dong Ku Kang

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5642

    摘要： Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage.

    摘要翻译： 提供了用于读取存储器数据的装置和使用其的方法。 用于读取存储器数据的装置包括存储多位信息的存储单元，从多位信息中检测多达位数信息作为预定位数的信息检测单元，控制位 基于来自信息检测单元的检测到的比特信息的存储器单元的源极线电压以及通过使用受控的源极线电压读取存储在存储器单元中的剩余位信息的剩余位信息读取单元。

    Memory devices and methods
    29.
    发明申请
    Memory devices and methods 有权
    内存设备和方法

    公开(公告)号：US20090231914A1

    公开(公告)日：2009-09-17

    申请号：US12232150

    申请日：2008-09-11

    申请人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

    发明人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

    IPC分类号： G11C16/06 ,  G11C16/00

    CPC分类号： G11C16/26 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5621

    摘要： Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.

    摘要翻译： 公开了一种存储器件和存储器数据读取方法。 存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔， 单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。 在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压 检测到错误位。

    Memory device and memory data reading method
    30.
    发明申请
    Memory device and memory data reading method 有权
    存储器和存储器数据读取方式

    公开(公告)号：US20090210776A1

    公开(公告)日：2009-08-20

    申请号：US12216744

    申请日：2008-07-10

    申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

    发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

    摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

    摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。