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105 条记录 (耗时 0.051 秒)

    Method for programming a multi-level non-volatile memory device
    21.
    发明授权
    Method for programming a multi-level non-volatile memory device 有权
    用于编程多级非易失性存储器件的方法

    公开(公告)号：US07596022B2

    公开(公告)日：2009-09-29

    申请号：US11848014

    申请日：2007-08-30

    申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

    发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C2211/5646

    摘要： A method for programming multi-level non-volatile memory. A plurality of multi-bit storage cells capable of storing different levels of charge usable to represent data represented by a least significant bits (LSBs) and a most significant bits (MSBs) are programmed first with LSBs and then with MSBs. The programmed storage cells have a threshold voltage lower than a voltage VR1 to store a first value, greater than VR1 and lower than a voltage VR2 to store a second value, and greater than VR2 and lower than a voltage VR3 to store a third value. Each of the cells has a threshold voltage greater than a voltage VR3 when it is desired that the storage cell store a fourth value. VR1 is less than VR2 which is less than VR3. The flag cell is programmed to have a threshold voltage greater than VR3 to indicate that the MSBs have been programmed.

    摘要翻译： 一种用于编程多级非易失性存储器的方法。 能够存储可用于表示由最低有效位（LSB）和最高有效位（MSB）表示的数据的不同电荷电平的多个多位存储单元首先用LSB编程，然后用MSB编程。 编程存储单元具有低于电压VR1的阈值电压，以存储大于VR1且低于电压VR2的第一值以存储第二值，并且大于VR2且低于电压VR3以存储第三值。 当期望存储单元存储第四值时，每个单元具有大于电压VR3的阈值电压。 VR1小于小于VR3的VR2。 标志单元被编程为具有大于VR3的阈值电压以指示MSB已被编程。

    Voltage reset circuits for a semiconductor memory device using option fuse circuit
    23.
    发明授权
    Voltage reset circuits for a semiconductor memory device using option fuse circuit 失效
    使用选项保险丝电路的半导体存储器件的电压复位电路

    公开(公告)号：US07505350B2

    公开(公告)日：2009-03-17

    申请号：US11642105

    申请日：2006-12-20

    申请人： Hee-Won Lee ,  Dae-Seok Byeon ,  Wook-Ghee Hahn

    发明人： Hee-Won Lee ,  Dae-Seok Byeon ,  Wook-Ghee Hahn

    IPC分类号： G11C17/18

    CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C16/04 ,  G11C17/18 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

    摘要： Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage associated with the voltage reset circuit is adjusted responsive to a state of the selected one of the plurality of fuses. A fusing control circuit generates the control signal to allow multiple adjustments of the output voltage by the voltage reset circuit. The option fuse circuit may be a plurality of option fuse circuits and the output voltage may be adjusted responsive to the states of the respective selected ones of the plurality of fuses of the option fuse circuits.

    摘要翻译： 用于半导体存储器件的电压调节器的控制电路包括选件熔丝电路和定影控制电路。 选项熔丝电路包括多个保险丝和选择电路，其根据控制信号选择多个保险丝之一。 响应于所选择的多个保险丝的状态来调整与电​​压复位电路相关联的输出电压。 熔断控制电路产生控制信号以允许电压复位电路对输出电压进行多次调节。 选项保险丝电路可以是多个选项保险丝电路，并且可以响应于选项保险丝电路的多个保险丝中的相应选择的保险丝的状态来调整输出电压。

    Method of Programming Flash Memory Device
    24.
    发明申请
    Method of Programming Flash Memory Device 失效
    闪存设备编程方法

    公开(公告)号：US20080019183A1

    公开(公告)日：2008-01-24

    申请号：US11833546

    申请日：2007-08-03

    申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

    发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

    IPC分类号： G11C16/02

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08

    摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.

    摘要翻译： 闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。 提供字线驱动程序以提高编程效率。 字线驱动器通过多个字线电耦合到存储器阵列。 字线驱动器包括多个通过电压开关。 这些开关具有由二极管电耦合到多个字线的输出。 编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。 顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

    Voltage regulator
    25.
    发明授权
    Voltage regulator 有权
    电压调节器

    公开(公告)号：US07315198B2

    公开(公告)日：2008-01-01

    申请号：US11167983

    申请日：2005-06-27

    申请人： Jin-Sung Park ,  Dae-Seok Byeon

    发明人： Jin-Sung Park ,  Dae-Seok Byeon

    IPC分类号： G05F1/575 ,  G05F1/56

    CPC分类号： G05F1/575

    摘要： Disclosed is a voltage regulator capable of reducing a set-up time. A driver is connected between a power supply terminal and the output terminal, and supplies a power supply voltage to the output terminal in response to a signal of a control node. A first signal generator provides a first signal to the control node when a voltage of the output terminal is lower than the target voltage. A second signal generator provides a second signal to the control node for a predetermined period of time when the voltage of the output terminal becomes higher than a detection voltage while the first signal generator is providing the first signal to the control node.

    摘要翻译： 公开了一种能够减少设置时间的电压调节器。 驱动器连接在电源端子和输出端子之间，并且响应于控制节点的信号将电源电压提供给输出端子。 当输出端子的电压低于目标电压时，第一信号发生器向控制节点提供第一信号。 当第一信号发生器向控制节点提供第一信号时，第二信号发生器在输出端的电压变得高于检测电压的预定时间段内向控制节点提供第二信号。

    High voltage generators having an integrated discharge path for use in non-volatile semiconductor memory devices
    27.
    发明授权
    High voltage generators having an integrated discharge path for use in non-volatile semiconductor memory devices 有权
    具有用于非易失性半导体存储器件的集成放电路径的高压发生器

    公开(公告)号：US07151702B2

    公开(公告)日：2006-12-19

    申请号：US10915294

    申请日：2004-08-10

    申请人： Wook-Ghee Han ,  Dae-Seok Byeon ,  Sung-Soo Lee ,  Young-Ho Lim

    发明人： Wook-Ghee Han ,  Dae-Seok Byeon ,  Sung-Soo Lee ,  Young-Ho Lim

    IPC分类号： G11C5/14

    CPC分类号： G11C16/12 ,  G11C5/145

    摘要： High voltage generators include a charge pump and a ripple reduction circuit that includes an integrated discharge path. The ripple reduction circuit limits the voltage level from a charge pump when the charge pump is in a first operating mode and provides a discharge path that from the output terminal of the ripple reduction circuit to the output of the charge pump when the charge pump is in a second operating mode. Semiconductor memories incorporating such high voltage generators are also provided. Coupling circuits having an integrated discharge path are also provided.

    摘要翻译： 高压发生器包括电荷泵和包括集成放电路径的纹波降低电路。 当电荷泵处于第一操作模式时，纹波降低电路限制来自电荷泵的电压电平，并且当电荷泵处于第一操作模式时提供从脉动降低电路的输出端子到电荷泵的输出的放电路径 第二种操作模式。 还提供了包括这种高电压发生器的半导体存储器。 还提供具有集成放电路径的耦合电路。

    Methods of Erasing Flash Memory Devices by Applying Wordline Bias Voltages Having Multiple Levels and Related Flash Memory Devices
    28.
    发明申请
    Methods of Erasing Flash Memory Devices by Applying Wordline Bias Voltages Having Multiple Levels and Related Flash Memory Devices 有权
    通过应用具有多个级别的字线偏置电压和相关闪存器件来擦除闪存器件的方法

    公开(公告)号：US20060279999A1

    公开(公告)日：2006-12-14

    申请号：US11381556

    申请日：2006-05-04

    申请人： Dae-Seok Byeon ,  Young-Ho Lim

    发明人： Dae-Seok Byeon ,  Young-Ho Lim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/16

    摘要： Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while applying an erasing voltage to a bulk region of memory cells, and verifying the erased states of the memory cells. Pursuant to these methods, the spread of the threshold-voltage distribution profile that may result from deviations of erasure-coupling ratios between memory cells may be reduced.

    摘要翻译： 提供擦除闪速存储器件中的数据的方法，其中产生多个字线偏置电压，其包括具有至少两个不同电平的字线偏置电压，通过将不同的字线偏置电压施加到多个字线中的相应字线来擦除数据 同时将擦除电压施加到存储器单元的主体区域，以及验证存储器单元的擦除状态。 根据这些方法，可能会降低可能由存储器单元之间的擦除耦合比的偏差导致的阈值 - 电压分布曲线的扩展。

    High-voltage generator circuit and semiconductor memory device including the same
    30.
    发明申请
    High-voltage generator circuit and semiconductor memory device including the same 有权
    高压发生器电路和包括其的半导体存储器件

    公开(公告)号：US20050128821A1

    公开(公告)日：2005-06-16

    申请号：US10977426

    申请日：2004-10-28

    申请人： Jong-Hwa Kim ,  Dae-Seok Byeon

    发明人： Jong-Hwa Kim ,  Dae-Seok Byeon

    IPC分类号： G11C16/06 ,  G11C5/14 ,  G11C11/407 ,  H01L27/10 ,  H02M3/07 ,  G11C5/00

    CPC分类号： H02M3/073 ,  H02M2001/0041

    摘要： According to embodiments of the invention, a high-voltage generator circuit may include a voltage detector block that has a voltage divider, a discharge section, a comparator, and a control signal generator. The voltage divider generates a divided voltage at an output node by dividing a high voltage. The discharge section discharges the high voltage to a power voltage in response to a first control signal. The comparator determines whether the divided voltage reaches a reference voltage, and the control signal generator generates a second control signal in response to an output from the comparator and the first control signal. The voltage divider may include a high-voltage prevention circuit that prevents the high voltage from being applied to a low-voltage transistor of the comparator during a discharge period of the high voltage. The high-voltage prevention circuit may include a depletion-type or enhancement-type NMOS transistor having a high breakdown voltage.

    摘要翻译： 根据本发明的实施例，高压发生器电路可以包括具有分压器，放电部分，比较器和控制信号发生器的电压检测器块。 分压器通过分压高电压在输出节点产生分压。 放电部分响应于第一控制信号将高电压放电到电源电压。 比较器确定分压是否达到参考电压，并且控制信号发生器响应于比较器的输出和第一控制信号产生第二控制信号。 分压器可以包括高电压防止电路，其在高电压的放电期间防止高电压施加到比较器的低压晶体管。 高压防止电路可以包括具有高击穿电压的耗尽型或增强型NMOS晶体管。