公开(公告)号：US5991880A

公开(公告)日：1999-11-23

申请号：US190053

申请日：1998-11-10

申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

IPC分类号： G06F12/14 ,  G06F21/00

CPC分类号： G06F21/76 ,  G06F12/1466

摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

摘要翻译： 用于解锁/锁定PLD的可覆盖的数据保护机制包括数据保护覆盖键寄存器，输入键寄存器和比较器。 在用户向输入键寄存器输入访问代码之后，软件程序向比较器发送使能信号，该比较器进一步比较存储在数据保护覆盖键寄存器中的位与输入键寄存器中的位。 如果两个寄存器中的位相同，则比较器输出禁用数据保护信号，从而允许用户修改该PLD中的配置数据。 在增加的版本控制号码和新的配置数据被下载到PLD之后，程序向比较器发送禁用信号，从而防止对该PLD的配置数据的进一步修改。

公开(公告)号：US5841867A

公开(公告)日：1998-11-24

申请号：US742711

申请日：1996-11-01

申请人： Neil G. Jacobson ,  Derek R. Curd

发明人： Neil G. Jacobson ,  Derek R. Curd

IPC分类号： G01R31/3185 ,  H04L9/00

CPC分类号： G01R31/318547 ,  G01R31/318516

摘要： The present invention provides an efficient programming verification system for Programmable Logic Devices (PLDs). Based upon IEEE JTAG standard boundary scan test architecture, the invention provides a novel test architecture including a configuration register and a signature analyzer coupled between the TDI and TDO pins of the JTAG architecture. The configuration register of the invention comprises three parts: an address register/counter, a data register, a status register. The address register/counter performs dual functions depending upon an instruction received by an instruction register. The invention eliminates the need to load each address sequentially into the address register/counter for programming by enabling the address register/counter to auto-increment the address for memory locations. After loading an initial address value, the address register/counter automatically increments the address for programming memory cells. To verify PLD programming, the invention applies a signature analyzer coupled between the TDI and TDO pins. A single input linear feedback shift register (SISR) or multiple LFSR (MISR) can be used to implement a signature analyzer in accordance with the invention. SISR or MISR uses a characteristic polynomial to generate a near-unique signature checksum for an input sequence. The accumulated signature checksum is then provided serially through the TDO pin for inspection.

摘要翻译： 本发明提供了一种用于可编程逻辑器件（PLD）的高效编程验证系统。 基于IEEE JTAG标准边界扫描测试架构，本发明提供了一种新颖的测试架构，包括配置寄存器和耦合在JTAG架构的TDI和TDO引脚之间的签名分析器。 本发明的配置寄存器包括三个部分：地址寄存器/计数器，数据寄存器，状态寄存器。 地址寄存器/计数器根据指令寄存器接收的指令执行双重功能。 本发明消除了通过使地址寄存器/计数器自动增加存储器位置的地址而将每个地址顺序地加载到地址寄存器/计数器中以进行编程的需要。 加载初始地址值后，地址寄存器/计数器自动递增编程存储单元的地址。 为了验证PLD编程，本发明应用了耦合在TDI和TDO引脚之间的签名分析器。 可以使用单输入线性反馈移位寄存器（SISR）或多个LFSR（MISR）来实现根据本发明的签名分析器。 SISR或MISR使用特征多项式来为输入序列生成近似唯一的签名校验和。 累积签名校验和然后通过TDO引脚提供串行检查。

公开(公告)号：US5831845A

公开(公告)日：1998-11-03

申请号：US52819

申请日：1998-03-31

申请人： Shi-dong Zhou ,  Derek R. Curd

发明人： Shi-dong Zhou ,  Derek R. Curd

IPC分类号： H02M3/18

CPC分类号： H02M3/073 ,  H02M2003/071

摘要： A voltage regulator for a charge pump is provided with two input paths from a reference input voltage to a comparator, each path having a node between a capacitor pair. The two paths are alternately initialized and used to control the charge pump which generates a reference output voltage, so that the reference output voltage tracks the reference input voltage at all times. Each path has its own capacitor divider and switching circuitry to alternately connect the nodes between the respective pairs of capacitors to the comparator, which compares the nodes to a second voltage reference. Since the circuit is alternately initialized, any alterations to the voltage introduced at the nodes between each of the two capacitor pairs, are corrected to the proper level within a short time.

摘要翻译： 用于电荷泵的电压调节器具有从参考输入电压到比较器的两个输入路径，每个路径具有电容器对之间的节点。 这两个路径被交替地初始化并用于控制产生参考输出电压的电荷泵，使得参考输出电压始终跟踪参考输入电压。 每个路径都有自己的电容分压器和开关电路，用于交替地将各对电容器之间的节点连接到比较器，比较器将节点与第二个参考电压进行比较。 由于电路被交替初始化，所以在两个电容器对中的每一个之间的节点处引入的电压的任何改变在短时间内被校正到适当的电平。

公开(公告)号：US5801548A

公开(公告)日：1998-09-01

申请号：US630321

申请日：1996-04-11

申请人： Napoleon W. Lee ,  Derek R. Curd

发明人： Napoleon W. Lee ,  Derek R. Curd

IPC分类号： H03K19/00 ,  H03K19/0185

CPC分类号： H03K19/0027

摘要： A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an input buffer, an output buffer and a reference generator. The input buffer includes a dedicated P-channel transistor connected in series with a dedicated N-channel transistor, and a plurality of trip-point adjustment transistors which are selectively connected in parallel with the dedicated transistors to adjust the trip-point of the input buffer by altering the N-to-P ratio. The output buffer includes two configurable buffers whose trip-points are also adjustable. A configurable reference generator is also provided for generating a high precision reference voltage which is supplied to the sense amplifiers located in the function blocks and interconnect matrix of the PLD.

摘要翻译： 一种可编程逻辑器件（PLD），包括用于在生产后改变PLD的速度 - 功率特性的可配置电路，并允许PLD选择性地在3.3伏或5伏电源上工作。 可配置电路包括输入缓冲器，输出缓冲器和参考发生器。 输入缓冲器包括与专用N沟道晶体管串联连接的专用P沟道晶体管，以及选择性地与专用晶体管并联的多个跳变点调整晶体管，以调整输入缓冲器的跳变点 通过改变N对P比例。 输出缓冲器包括两个可配置的缓冲器，其跳变点也可调。 还提供了可配置的参考发生器，用于产生高精度参考电压，其被提供给位于PLD的功能块和互连矩阵中的读出放大器。

公开(公告)号：US5561631A

公开(公告)日：1996-10-01

申请号：US397821

申请日：1995-03-03

申请人： Derek R. Curd

发明人： Derek R. Curd

IPC分类号： G11C16/34 ,  G11C29/34 ,  G11C29/52 ,  H03K19/177 ,  G11C16/02

CPC分类号： G11C16/3445 ,  G11C16/344 ,  G11C29/34 ,  G11C29/52 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764

摘要： A programmable logic device (PLD) performs a self-test erase check operation on memory elements to verify if the PLD is completely erased. The output signals of the sense amplifiers associated with the PLD bitlines drive a plurality of NMOS devices. The NMOS devices share a common source (node), thereby providing in effect an n-input NOR gate, where n is the number of bitlines in the array. The memory cells associated with an entire wordline of the PLD memory array are simultaneously checked for an erased state by bringing the wordline under test high while keeping all other wordlines low. If all of the memory cells on a wordline are erased, every sense amplifier output is low, all of the NMOS devices are off, and the output signal of the NOR gate is high due to a weak pull-up on the common node, thereby indicating that the whole column is properly erased. If one or more memory cells on the selected wordline are not completely erased, then at least one sense amplifier output is high because the cell is not able to pull its bitline low to switch the sense amplifier. The high output of the sense amplifier turns on its associated NMOS device, thereby pulling down the voltage on the common node and providing a low output signal from the NOR gate, thereby indicating that additional erasing of the array is necessary.

摘要翻译： 可编程逻辑器件（PLD）对存储器元件执行自检擦除检查操作，以验证PLD是否被完全擦除。 与PLD位线相关联的读出放大器的输出信号驱动多个NMOS器件。 NMOS器件共享公共源（节点），从而实际上提供了n个输入的或非门，其中n是阵列中的位线数。 与PLD存储器阵列的整个字线相关联的存储器单元通过将字线检测为高电平同时保持所有其他字线低的情况而被同时检查擦除状态。 如果字线上的所有存储单元被擦除，则每个读出放大器的输出都为低电平，所有的NMOS器件都关闭，由于公共节点上的弱上拉，NOR门的输出信号为高电平，因此 表明整列被正确擦除。 如果所选字线上的一个或多个存储单元未被完全擦除，则至少一个读出放大器输出为高，因为单元不能将其位线拉低以切换读出放大器。 读出放大器的高输出导通其相关联的NMOS器件，从而降低公共节点上的电压，并提供来自或非门的低输出信号，从而指示阵列的额外擦除是必需的。

公开(公告)号：US5561629A

公开(公告)日：1996-10-01

申请号：US402454

申请日：1995-03-10

申请人： Derek R. Curd

发明人： Derek R. Curd

IPC分类号： G11C16/26 ,  G11C7/00

CPC分类号： G11C16/26

摘要： A sense amplifier is provided that automatically determines its enabled/disabled state. The sense amplifier includes a latch to store the enable/disable signals. A global power-on-reset signal during initialization sets the state of this latch to a default configuration which disables, i.e. powers down, the sense amplifier. During configuration, an active latch enable signal forces the sense amplifier into an enable ready state. Then, a high signal is provided to each wordline associated with the bitline of the sense amplifier. This causes any erased memory cell driven by the wordlines to pull the associated bitline into a bitline low state and causes the sense amplifier output signal to switch states. This switch causes the latch to be overwritten with the opposite state, thereby enabling the sense amplifier. When the latch enable signal goes inactive after configuration of the device, the latch is set such that the sense amplifier remains enabled, i.e. powered up. If there are no erased cells on the bitline, i.e. all of the cells are programmed, then the sense amplifier output signal remains the same, and the latch is not overwritten. Thus, when the latch enable signal returns to a high state, the sense amplifier remains disabled. Therefore, any sense amplifier that is not needed in the design, indicated by the lack of erased memory cells, remains disabled. In this manner, the present invention advantageously powers down all unused sense amplifiers automatically, thereby significantly reducing power consumption and minimizing overhead while maximizing the programmability of the device.

摘要翻译： 提供了一种自动确定其启用/禁用状态的读出放大器。 读出放大器包括用于存储使能/禁止信号的锁存器。 在初始化期间，全局上电复位信号将该锁存器的状态设置为默认配置，该默认配置禁用读出放大器的功率下降。 在配置期间，有源锁存使能信号强制读出放大器进入使能就绪状态。 然后，向与读出放大器的位线相关联的每个字线提供高信号。 这导致由字线驱动的任何被擦除的存储器单元将相关联的位线拉到位线低状态，并使读出放大器输出信号切换状态。 该开关使得锁存器以相反的状态被覆盖，从而使得读出放大器成为可能。 当锁存器使能信号在器件配置之后变为无效时，锁存器被设置为使得读出放大器保持使能，即加电。 如果位线上没有擦除的单元，即所有单元都被编程，则读出放大器输出信号保持相同，并且锁存器不被覆盖。 因此，当锁存使能信号返回到高电平状态时，读出放大器保持禁止。 因此，由缺少擦除的存储单元指示的设计中不需要的任何读出放大器仍然禁用。 以这种方式，本发明有利地自动地关闭所有未使用的读出放大器，从而显着降低功耗并最大限度地降低开销，同时最大限度地提高器件的可编程性。