公开(公告)号：US6025631A

公开(公告)日：2000-02-15

申请号：US198876

申请日：1998-11-24

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L23/50 ,  H01L23/60 ,  H01L23/48

CPC classification number: H01L23/50 ,  H01L23/60 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/13034 ,  H01L2924/13091 ,  H01L2924/14

Abstract: An ESD protective device for protection of an integrated circuit (IC) package from electrostatic discharge damage. The ESD protective device protects the internal circuit of the IC connected to wired pins of the IC package against ESD damage due to ESD stress in neighboring no-connect pins. The ESD protective device includes an ESD protective unit coupled to the power bus and a bonding pad coupled between this ESD protective device and the no-connect pin. The ESD protective unit causes ESD stress applied to the no-connect pin to be diverted to the power bus, thus preventing ESD transfer between a no-connect pin and an active pin, which could damage the internal circuit.

Abstract translation: 一种用于保护集成电路（IC）封装免受静电放电损坏的ESD保护装置。 ESD保护装置保护连接到IC封装的有线引脚的IC的内部电路，防止由于相邻不连接引脚中的ESD应力而导致的ESD损坏。 ESD保护装置包括耦合到电源总线的ESD保护单元和耦合在该ESD保护装置和无连接引脚之间的接合焊盘。 ESD保护单元会使施加到无连接引脚的ESD应力转移到电源总线，从而防止无连接引脚和有源引脚之间的ESD传输，这可能会损坏内部电路。

公开(公告)号：US06002156A

公开(公告)日：1999-12-14

申请号：US931594

申请日：1997-09-16

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/76

CPC classification number: H01L27/0277 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/0619 ,  H01L29/0692 ,  H01L2924/0002

Abstract: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate. The gate-to-source diffusion edges are continuous along the gate body, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. The angled gate segments provide a total gate-to-area ratio greater than that of a multi-finger-gate configuration within an equal size active region. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

公开(公告)号：US5955763A

公开(公告)日：1999-09-21

申请号：US931343

申请日：1997-09-16

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0274 ,  H01L2924/0002

Abstract: A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate. The gate/channel-to-drain and gate/channel-to-source diffusion edges are continuous along the gate/channel layout, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

Abstract translation: 多栅指MOSFET结构将栅极元件定位在漏极和源极扩散区域之间的沟道上，使得整个结构在衬底中的有源区域内。 栅极/沟道至漏极和栅极/沟道至源极扩散边缘沿着栅极/沟道布局是连续的，以便级联反弹作用以增强ESD事件期间整个栅极元件的均匀导通 。 此外，当MOSFET用作高电流驱动CMOS输出缓冲器时，栅极信号RC延迟足以提供输出电压的噪声抑制。

公开(公告)号：US4509012A

公开(公告)日：1985-04-02

申请号：US454690

申请日：1982-12-30

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G01R31/26 ,  G01R27/26

CPC classification number: G01R31/26

Abstract: First and second voltage sweeps are applied to a metal-insulator-semiconductor device with the device in a deep depletion mode during at least a portion of each sweep. Capacitance-voltage characteristics of the device are determined for at least a portion of each sweep while the device is in the deep depletion mode. Minority carrier generation parameters of the device in the deep depletion mode are determined based on the capacitance-voltage characteristics for the first and second voltage sweeps.

Abstract translation: 在每次扫描的至少一部分期间，第一和第二电压扫描被施加到金属 - 绝缘体 - 半导体器件，器件处于深度耗尽模式。 当器件处于深度耗尽模式时，器件的电容 - 电压特性被确定为每次扫描的至少一部分。 基于第一和第二电压扫描的电容 - 电压特性来确定深耗尽模式中的器件的少数载波产生参数。

公开(公告)号：US06858900B2

公开(公告)日：2005-02-22

申请号：US09973291

申请日：2001-10-08

Applicant: Wei-Fan Chen ,  Shi-Tron Lin ,  Chuan-Jane Chao

Inventor： Wei-Fan Chen ,  Shi-Tron Lin ,  Chuan-Jane Chao

IPC: H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L29/06 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L27/027 ,  H01L29/0692

Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract translation: 在本发明中提供ESD保护装置及其形成方法。 通过采用通过双栅极氧化工艺和击穿增强层制造的薄栅氧化物，提供具有较低触发电压的ESD保护器件。 根据本发明的用于ESD保护的NMOS结构具有岛，控制栅和击穿增强层。 这些岛以及与NMOS的漏极区重叠的击穿增强层减小漏极区中的PN结的击穿电压，从而降低ESD触发电压并提高NMOS的ESD保护水平。 此外，本发明可应用于一般集成电路工艺以及各种ESD保护器件。

公开(公告)号：US06664599B1

公开(公告)日：2003-12-16

申请号：US10281660

申请日：2002-10-28

Applicant: Wei-Fan Chen ,  Shi-Tron Lin

Inventor： Wei-Fan Chen ,  Shi-Tron Lin

IPC: H01L2362

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) protection device has a semiconductor bulk of a first conductivity type, a first doped region of a second conductivity type formed in the semiconductor bulk, a second doped region of a second conductivity type formed in the semiconductor bulk, a channel region formed between the first doped region and the second doped region, a plurality of contacts formed on the first doped region, and a well of the second conductivity type formed in the semiconductor bulk and positioned between the channel and the contacts.

Abstract translation: 静电放电（ESD）保护装置具有第一导电类型的半导体本体，形成在半导体本体中的第二导电类型的第一掺杂区，形成在半导体本体中的第二导电类型的第二掺杂区，沟道 形成在第一掺杂区域和第二掺杂区域之间的多个触点，形成在第一掺杂区域上的多个触点以及形成在半导体本体中并位于沟道和触点之间的第二导电类型的阱。

公开(公告)号：US06628160B2

公开(公告)日：2003-09-30

申请号：US09798977

申请日：2001-03-06

Applicant: Shi-Tron Lin ,  Yung-Chow Peng

Inventor： Shi-Tron Lin ,  Yung-Chow Peng

IPC: H03K301

CPC classification number: H03K19/01707 ,  H01L27/092 ,  H01L29/78609 ,  H03K19/0016

Abstract: For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

Abstract translation: 对于集成电路中的MOSFET的低电压和高速操作，向源节点施加小的电压，从而导致源极结的轻微的正向偏压，从而降低其阈值电压。 由于源节点偏置和物体效应的组合效应，阈值电压的降低大于施加的源极电压的绝对值。 通过简单地将偏置电压施加到身体（井），可以提高性能。 可以使用事件的检测来仅在需要时将性能提升应用于集成电路中的关键路径。 当检测到逻辑事件确定信号在此后不久将传播通过关键路径时，关键路径中的电路元件的源节点偏置可以及时调整以提高速度。 然而，当没有信号通过关键路径时，源保持在另一个潜力，以便在不提升速度时节省功率。

公开(公告)号：US06552594B2

公开(公告)日：2003-04-22

申请号：US09437817

申请日：1999-11-10

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H03L500

CPC classification number: H01L27/0255 ,  H01L27/0288

Abstract: The present invention provides a buffer for voltage ringing and overshooting suppression that improves the ESD protection. The buffer comprises a transistor and a resistance modulator. The resistance modulator is connected in series between an IC pad and a power node. The resistance modulator provides a first resistance during normal circuit operation, and provides a second resistance that is lower than the first resistance during an ESD event.

Abstract translation: 本发明提供了用于电压振荡和过冲抑制的缓冲器，其改善了ESD保护。 缓冲器包括晶体管和电阻调制器。 电阻调制器串联连接在IC焊盘和电源节点之间。 电阻调制器在正常电路操作期间提供第一电阻，并且在ESD事件期间提供低于第一电阻的第二电阻。

公开(公告)号：US06542346B1

公开(公告)日：2003-04-01

申请号：US09586568

申请日：2000-06-02

Applicant: Wei-Fan Chen ,  Shu-Chuan Lee ,  Ta-Lee Yu ,  Shi-Tron Lin

Inventor： Wei-Fan Chen ,  Shu-Chuan Lee ,  Ta-Lee Yu ,  Shi-Tron Lin

IPC: H02H322

CPC classification number: H01L27/0251 ,  H01L29/7436 ,  H01L29/87

Abstract: A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input buffer of the present invention comprises a voltage-sharing circuit and a switch circuit, wherein the voltage-sharing circuit is connected between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. The switch circuit is connected to the voltage-sharing circuit and comprises a control gate to control the switching operation of the switch circuit according to the reference voltage. The present invention can be implemented to solve the rapid gate oxide aging problem without incurring any change in the original process flow by employing a voltage-sharing circuit.

Abstract translation: 连接到集成电路的焊盘的高压公差输入缓冲器和高压ESD保护电路，用于防止快速栅极氧化物老化。 本发明的高电压公差输入缓冲器包括电压共享电路和开关电路，其中电压共享电路连接在焊盘和电源轨之间，并产生不高于焊盘电压的参考电压 。 开关电路连接到分压电路，并包括控制栅极，以根据参考电压来控制开关电路的开关操作。 本发明可以实现以解决快速栅极氧化物老化问题，而不会通过采用电压共享电路而引起原始工艺流程的任何变化。

公开(公告)号：US06489672B2

公开(公告)日：2002-12-03

申请号：US09742695

申请日：2000-12-19

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L2348

CPC classification number: H01L23/60 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An IC package architecture with electrostatic discharge (ESD) protection is provided for use on an IC package for the purpose of allowing the ESD robustness of the IC package to be farther enhanced and the structural complexity of the same to be further simplified as compared to the prior art. The IC package includes a lead frame having a die pad for mounting an IC chip thereon, a plurality of package pins with some no-connect pins which are grouped into at least one no-connect pin unit, each unit consisting of one single no-connect pin or a number or consecutively arranged no-connect pins. ESD protection can be provided to any no-connect pin unit on the IC package either by arranging a pair of power pins proximate to the respective sides of the no-connect pin unit; by arranging a power pin proximate to one side of the no-connect pin unit and an elongated conductive tongue proximate to the other side; or by arranging a pair of elongated conductive tongues proximate to the respective sides of the no-connect pin unit. This provides ESD protection to all the no-connect pins in the no-connect pin unit without having to connect them to ESD protection circuits.

Abstract translation: 提供了具有静电放电（ESD）保护功能的IC封装体系结构，用于IC封装，目的是使IC封装的ESD稳健性进一步提高，并将其结构复杂性进一步简化为与 现有技术 IC封装包括具有用于在其上安装IC芯片的管芯焊盘的引线框架，具有一些无连接引脚的多个封装引脚，其被组合成至少一个无连接引脚单元，每个单元由一个单独的无连接引脚组成， 连接引脚或数字或连续排列的无连接引脚。 可以通过在靠近无连接引脚单元的相应侧面布置一对电源引脚来将ESD保护提供给IC封装上的任何无连接引脚单元; 通过布置靠近所述无连接销单元的一侧的电源销和靠近另一侧的细长导电舌片; 或者通过布置靠近无连接销单元的相应侧面的一对细长导电舌片。 这为无连接引脚单元中的所有无连接引脚提供ESD保护，而无需将其连接到ESD保护电路。