公开(公告)号：US6078585A

公开(公告)日：2000-06-20

申请号：US619966

申请日：1996-03-20

Applicant: Satoshi Kakuma ,  Shiro Uriu

Inventor： Satoshi Kakuma ,  Shiro Uriu

IPC: H04Q3/00 ,  H04L12/931 ,  H04L12/933 ,  H04L12/937 ,  H04Q1/04 ,  H04Q3/68 ,  H04L12/56

CPC classification number: H04L12/5601 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/455 ,  H04Q3/68

Abstract: Four SR modules are provided in the second stage of a 3-stage MSSR switch. To guarantee the MSSR switch the capacity of 20 Gbps, SR modules are provided in each of the first and third stages of the switch. When the capacity of the MSSR switch is extended from 20 Gbps to 40 Gbps, SR modules are added to both of the first and third stages and connected to the four SR modules in the second stage. To further extend the capacity of the MSSR switch to 60 or 80 Gbps, the SR modules are sequentially added to the first and third stages, and the newly provided SR modules are connected to the four SR modules in the second stage.

Abstract translation: 在三级MSSR开关的第二级提供四个SR模块。 为了保证MSSR的交换容量为20Gbps，SR模块在交换机的第一和第三级提供。 当MSSR交换机的容量从20Gbps扩展到40Gbps时，SR模块将被添加到第一和第三级，并连接到第二级的四个SR模块。 为了进一步将MSSR交换机的容量扩展到60G或80Gbps，SR模块依次添加到第一级和第三级，新提供的SR模块连接到第二级的四个SR模块。

公开(公告)号：US07774580B2

公开(公告)日：2010-08-10

申请号：US11077561

申请日：2005-03-11

Applicant: Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

Inventor： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F15/8007

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract translation: 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

公开(公告)号：US06789176B2

公开(公告)日：2004-09-07

申请号：US09286332

申请日：1999-04-05

Applicant: Shiro Uriu ,  Masanobu Furukoshi ,  Tetsuaki Wakabayashi ,  Kazumasa Sonoda

Inventor： Shiro Uriu ,  Masanobu Furukoshi ,  Tetsuaki Wakabayashi ,  Kazumasa Sonoda

IPC: G06F1206

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L2012/5681

Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.

Abstract translation: 在具有简单布置的公共缓冲装置中，在接收到多地址呼叫时，可以从缓冲存储器高效地释放写入地址。 对于要发送到特定线路的ATM信元，在公共缓冲存储器中设置写入地址，并且将ATM信元写入写入地址。 ATM单元从对应于写入地址的地址读取，并被发送到特定的行。 然后，释放相关的写入地址。 在写入表中输入多个多地址线，在公共缓冲设备中以特定地址写入的ATM信元可以跨多路地址线进行组播。 每当从特定地址读取ATM信元时，将读取控制表中的ATM信元的发送指定行与设置在写入控制表中的多地址线进行比较。 当行匹配时，释放写入控制表中设置的ATM信元的写入地址。

公开(公告)号：US5555265A

公开(公告)日：1996-09-10

申请号：US332379

申请日：1994-10-31

Applicant: Satoshi Kakuma ,  Shiro Uriu ,  Noriko Samejima ,  Kazuo Hajikano

Inventor： Satoshi Kakuma ,  Shiro Uriu ,  Noriko Samejima ,  Kazuo Hajikano

IPC: H04Q3/00 ,  H04L12/813 ,  H04L12/815 ,  H04L12/863 ,  H04L12/911 ,  H04L12/931 ,  H04L12/56

CPC classification number: H04L49/505 ,  H04L12/5693 ,  H04L47/10 ,  H04L47/522 ,  H04L47/6215 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/3081 ,  H04L49/9036 ,  H04L49/9078 ,  H04L2012/5651 ,  H04L2012/5672 ,  H04L2012/5681 ,  H04L49/253 ,  H04L49/30

Abstract: A switching path setting system is disposed between an input line connected to switching equipment and a switch. An input interface device allocates a cell to a quality class as tag information corresponding to an identifier of the cell. A quality class buffer stores the cell corresponding to the quality class allocated by the input interface device corresponding to the quality class. A cell is read from the quality class buffer at a band allocated to each quality class.

Abstract translation: 开关路径设定系统设置在与开关装置连接的输入线与开关之间。 输入接口设备将小区分配给质量类作为与小区的标识符相对应的标签信息。 质量类缓冲器存储与由质量等级对应的由输入接口设备分配的质量等级对应的单元。 在分配给每个质量等级的频带上从质量等级缓冲器读取单元。

公开(公告)号：US07453800B2

公开(公告)日：2008-11-18

申请号：US10020077

申请日：2001-10-30

Applicant: Ryo Takajitsuko ,  Kenichi Okabe ,  Shiro Uriu ,  Hiroya Kawasaki

Inventor： Ryo Takajitsuko ,  Kenichi Okabe ,  Shiro Uriu ,  Hiroya Kawasaki

IPC: H04L12/56

CPC classification number: H04L49/3081 ,  H04L49/1523 ,  H04L49/30 ,  H04L49/506 ,  H04L2012/5635

Abstract: A communications apparatus for switching among different interfaces includes a switch unit. The switch unit includes a main switch for switching data of a fixed length and an interface having a first buffer for an input of the main switch and a second buffer for an output of the main switch.

Abstract translation: 用于在不同接口之间切换的通信装置包括开关单元。 开关单元包括用于切换固定长度的数据的主开关和具有用于主开关的输入的第一缓冲器和用于主开关的输出的第二缓冲器的接口。

公开(公告)号：US20060004994A1

公开(公告)日：2006-01-05

申请号：US11070327

申请日：2005-03-03

Applicant: Shiro Uriu ,  Mitsuharu Wakayoshi

Inventor： Shiro Uriu ,  Mitsuharu Wakayoshi

IPC: G06F9/00

CPC classification number: G06F15/7867

Abstract: A processor executes a predetermined operation process by switching a connection structure between a plurality of arithmetic and logic unit modules. Each of the arithmetic and logic unit modules includes a plurality of arithmetic and logic units. The arithmetic and logic unit modules include a first arithmetic and logic unit module that includes a plurality of arithmetic and logic units that executes various operation processes, and a second arithmetic and logic unit module that includes a plurality of arithmetic and logic units of which executable operation processes are limited compared with the first arithmetic and logic unit module.

Abstract translation: 处理器通过切换多个算术和逻辑单元模块之间的连接结构来执行预定的操作处理。 每个算术和逻辑单元模块包括多个算术和逻辑单元。 算术和逻辑单元模块包括第一算术和逻辑单元模块，其包括执行各种操作过程的多个算术和逻辑单元，以及包括多个算术和逻辑单元的第二算术和逻辑单元模块，其中可执行操作 与第一个算术和逻辑单元模块相比，过程是有限的。

公开(公告)号：US06510165B1

公开(公告)日：2003-01-21

申请号：US08626699

申请日：1996-04-02

Applicant: Shiro Uriu ,  Norio Suzuki ,  Noriko Samejima

Inventor： Shiro Uriu ,  Norio Suzuki ,  Noriko Samejima

IPC: H04L1256

CPC classification number: H04L49/104 ,  H04L12/5601 ,  H04L49/309 ,  H04L2012/562 ,  H04L2012/5635 ,  H04L2012/5651

Abstract: A service identification adding portion adds service identification information to a cell corresponding to each connection that uses a predetermined communication service (ABR service) and that is input to a switch system. A connection number counting portion counts the number of connections that use the communication service on each output line at predetermined intervals. A band control information generating portion generates band control information corresponding to each output line at predetermined intervals based on the number of connections counted at predetermined intervals. A band control information indicating portion sends band control information at predetermined intervals corresponding to each output line to a transmission side terminal corresponding to a connection that uses the communication service on each output line.

Abstract translation: 服务识别添加部分将服务识别信息添加到与使用预定通信服务（ABR服务）的每个连接相对应的小区，并且被输入到交换机系统。 连接号码计数部分以预定间隔对每个输出线上使用通信服务的连接数进行计数。 频带控制信息生成部基于以预定间隔计数的连接数，以规定间隔生成与各输出线对应的频带控制信息。 频带控制信息指示部分将与每条输出线对应的预定间隔的频带控制信息发送到对应于在每个输出线上使用通信服务的连接的发送侧终端。

公开(公告)号：US06430157B1

公开(公告)日：2002-08-06

申请号：US09047815

申请日：1998-03-25

Applicant: Shiro Uriu ,  Kazumasa Sonoda ,  Hiroshi Ishiwata

Inventor： Shiro Uriu ,  Kazumasa Sonoda ,  Hiroshi Ishiwata

IPC: H04L1200

CPC classification number: H04L12/5601 ,  H04L2012/5635

Abstract: A switching system in an ATM switching system accommodating an ABR is constructed of an individual units connected to a transmitting terminal or a receiving terminal to implement an efficient bandwidth authorization, and a plurality of intra-system relay devices having transmission allowed rate calculating units. In this switching system, there are separated a transfer of a management cell between the transmitting terminal or the receiving terminal and the individual unit and a transfer of the management cell between the plurality of intra-system relay devices.

Abstract translation: 容纳ABR的ATM交换系统中的交换系统由连接到发送终端或接收终端的各个单元构成，以实现有效的带宽授权，以及具有发送允许率计算单元的多个系统内中继设备。 在该交换系统中，分离了发送终端或接收终端与各个单元之间的管理单元的传送，以及多个系统内中继设备之间的管理单元的传送。

公开(公告)号：US5726987A

公开(公告)日：1998-03-10

申请号：US621804

申请日：1996-03-22

Applicant: Shiro Uriu ,  Kenichi Okabe ,  Satoshi Kakuma

Inventor： Shiro Uriu ,  Kenichi Okabe ,  Satoshi Kakuma

IPC: H04Q3/00 ,  H04L12/70 ,  H04L12/801 ,  H04L12/835 ,  H04L12/861 ,  H04L12/911 ,  H04L12/28

CPC classification number: H04L12/5602 ,  H04L49/108 ,  H04L2012/5636 ,  H04L2012/5682

Abstract: A congestion-monitor control apparatus monitors a congestion condition of each output highway in an asynchronous transfer mode switching system transferring cells to output highways by using a cell-storage buffer. The apparatus includes a monitor circuit monitoring the number of cells stored in the cell-storage buffer for each output highway at a plurality of timings during a given monitor time interval. The apparatus further includes a first determination circuit comparing the number of times when the number of cells from the monitor circuit is equal to or more than a first threshold value during the given monitor time interval with a second threshold value and determining whether the congestion has occurred in a corresponding output highway based on a comparison result.

Abstract translation: 拥塞监视控制装置通过使用小区存储缓冲器来监视异步传送模式切换系统中的每个输出高速公路的拥堵情况，该异步传输模式切换系统通过使用小区存储缓冲器将小区传送到输出高速公路。 该装置包括在给定的监视时间间隔期间以多个定时监视每个输出高速公路存储在单元存储缓冲器中的单元的数量的监视器电路。 该装置还包括第一确定电路，其比较在具有第二阈值的给定监视时间间隔期间来自监视电路的单元数量等于或大于第一阈值的次数，并且确定是否已发生拥塞 在相应的输出高速公路上基于比较结果。

公开(公告)号：US5675587A

公开(公告)日：1997-10-07

申请号：US758061

申请日：1996-11-27

Applicant: Yuzo Okuyama ,  Satoshi Kakuma ,  Shiro Uriu ,  Kazuo Hajikano

Inventor： Yuzo Okuyama ,  Satoshi Kakuma ,  Shiro Uriu ,  Kazuo Hajikano

IPC: H04Q3/00 ,  H04L12/28 ,  H04L12/70 ,  H04Q11/04 ,  G06F11/00

CPC classification number: H04L12/5601 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/555 ,  H04Q11/0478 ,  H04L2012/5628 ,  H04L2012/5636 ,  H04L2012/5647 ,  H04L2012/5652

Abstract: A test cell generating section periodically generates a pass determining test cell at preset timing, multiplexes them with user cells from a user line interface, and transmits the result of multiplexing to an ATM exchange. When no user cell is supplied from the user line interface, the test cell generating section transmits only the pass determining test cell to the ATM exchange. A cell determining section determines whether a cell supplied from the ATM exchange is a user cell or test cell, identifies/determines the pass based on information of the test cell and outputs only the user cell to the user line side when the supplied cell is the test cell.

Abstract translation: 测试小区生成部分在预定的定时周期性地生成通过确定测试小区，并将其与用户线路接口的用户小区进行复用，并将多路复用结果发送到ATM交换机。 当用户线路接口没有提供用户小区时，测试小区生成部分仅将通过确定测试小区发送到ATM交换机。 小区确定部分确定从ATM交换机提供的小区是否是用户小区或测试小区，当所提供的小区为所述小区时，基于所述测试小区的信息来识别/确定所述通过，并且仅将所述用户小区仅输出到所述用户线路侧 测试单元。