公开(公告)号：US06469540B2

公开(公告)日：2002-10-22

申请号：US09880018

申请日：2001-06-14

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/17792

摘要： A reconfigurable device includes a plurality of function cells and a programmable interconnect network which programmably connects the function cells. The programmable interconnect network includes horizontal programmable interconnect ways and vertical programmable interconnect ways. Each horizontal programmable interconnect way includes a short horizontal programmable interconnect channel and a long horizontal programmable interconnect channel, and each vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel. In the horizontal programmable interconnect way, both the short horizontal programmable interconnect channel and the long horizontal programmable interconnect channel are constructed to have “shift structure”, thereby “sector segmentation” and problems related to the sector segmentation are avoided. The function cells are directly connected to the short horizontal programmable interconnect channel, but are not directly connected to the long horizontal programmable interconnect channel, therefore, signal transfer of input/output signals between the function cell and the long horizontal programmable interconnect channel is conducted necessarily through the short horizontal programmable interconnect channel and a programmable switch, thereby load capacitance on the long horizontal programmable interconnect channel is reduced and thereby high-speed signal transfer is realized.

摘要翻译： 可重构设备包括多个功能单元和可编程地连接功能单元的可编程互连网络。 可编程互连网络包括水平可编程互连方式和垂直可编程互连方式。 每个水平可编程互连方式包括一个短的水平可编程互连通道和一个长的水平可编程互连通道，每个垂直可编程互连方式包括一个短的垂直可编程互连通道和一个长的垂直可编程互连通道。 在水平可编程互联方式中，短水平可编程互连通道和长水平可编程互连通道被构造为具有“移位结构”，从而避免了“扇区分割”，并且避免了与扇区分割相关的问题。 功能单元直接连接到短水平可编程互连通道，但不直接连接到长水平可编程互连通道，因此必须执行功能单元和长水平可编程互连通道之间的输入/输出信号的信号传输 通过短水平可编程互连通道和可编程开关，从而减小了长水平可编程互连通道上的负载电容，从而实现了高速信号传输。

公开(公告)号：US06188240B1

公开(公告)日：2001-02-13

申请号：US09325339

申请日：1999-06-04

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K1920

CPC分类号： G06F7/503 ,  G06F2207/3876 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first through third configuration input terminals, a core logic carry output terminal, a core logic carry generation output terminal, a core logic carry propagation output terminal, a ripple-core logic carry input terminal, and a sum output terminal. Connected to interconnection wires and the first and the second argument input groups, an input block includes eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0”. Connected to the first through the third configuration input terminals, respectively, first through third memory circuits stores, as first through third stored logic values, a logic value of one bit. A carry logic circuit has a ripple carry input terminal, a ripple carry output terminal, a ripple-core logic carry output terminal, a core logic carry generation input terminal, and a core logic carry propagation input terminal.

摘要翻译： 可编程功能块包括具有由第一到第四参数输入端子组成的第一参数输入组的核心逻辑电路，由第一至第四参数输入端子组成的第二参数输入组，第一至第三配置输入端子， 终端，核心逻辑携带产生输出终端，核心逻辑携带传播输出终端，纹波核心逻辑进位输入终端和和输出终端。 连接到互连线和第一和第二自变量输入组，输入块包括第八输入选择单元，用于在互连线上选择八个输入选择的信号中的八个信号，固定逻辑值“1”，以及 固定逻辑值为“0”。 第一至第三存储电路分别连接到第一至第三配置输入端，作为第一至第三存储逻辑值，存储一位的逻辑值。 进位逻辑电路具有纹波输入端子，纹波输入端子，纹波纹逻辑输入端子，核心逻辑进位产生输入端子和核心逻辑进位传播输入端子。

公开(公告)号：US09071889B2

公开(公告)日：2015-06-30

申请号：US13637823

申请日：2011-02-08

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G08B21/00 ,  H04Q9/00 ,  G06K19/07 ,  B25J13/08

CPC分类号： H04Q9/00 ,  B25J13/081 ,  G01D18/00 ,  G01D21/00 ,  G06K19/0717 ,  H04Q2209/47

摘要： A radio tag sensor system includes a plurality of radio tag sensor chips, which incorporate respective sensors, store unique identification numbers, a plurality of micro base stations, and a central processing unit which perform communications with the micro base stations via a connection network. Each of the micro base stations performs wireless communications with and wirelessly supplies electric power to only those of the radio tag sensor chips which are disposed in an assigned region thereof. Each of the assigned regions includes at least one radio tag sensor chip which is not included in the other assigned regions. The central processing unit controls the communications via the connection network. The central processing unit collects the sensed values from sensors of the radio tag sensor chips through the micro base stations, generates a spatial distribution map of the sensed values, and updates the spatial distribution map with time.

摘要翻译： 无线电标签传感器系统包括多个无线电标签传感器芯片，其包含各自的传感器，存储唯一的标识号，多个微型基站和经由连接网络与微型基站进行通信的中央处理单元。 微基站中的每一个都执行无线通信，并且仅将电力提供给仅布置在其分配区域中的无线电标签传感器芯片的电力。 每个分配的区域包括至少一个不包括在其他分配区域中的无线电标签传感器芯片。 中央处理单元通过连接网络控制通信。 中央处理单元通过微基站收集来自无线电标签传感器芯片的传感器的感测值，生成感测值的空间分布图，随时间更新空间分布图。

公开(公告)号：US08878566B2

公开(公告)日：2014-11-04

申请号：US13821892

申请日：2011-08-18

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H01L27/101 ,  H03K19/177 ,  H03K19/17744 ,  H03K19/17748

摘要： A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmable wiring group. The reconfigurable circuit is also characterized in being provided with a fourth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the functional block input wiring group, and/or a fifth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the branch lines of the functional block output wiring.

摘要翻译： 本发明的可重构电路的特征在于具有：沿第一方向设置的第一可编程布线组; 第二可编程布线组，其沿与第一方向相交的第二方向设置; 第一开关元件阵列，其在功能块输入布线组的第一可编程布线组和分支线组的交叉点处或在第一可编程布线组的分支线组的交叉点处，在第一 可编程接线组和功能块输入接线组; 第二开关元件阵列，其在第一可编程布线组和功能块输出布线的交叉点处将可编程布线组彼此连接; 以及第三开关元件阵列，其在第二可编程布线组和第一可编程布线组的交叉点处将可编程布线组彼此连接。 可重构电路的特征还在于具有第四开关元件阵列，该第四开关元件阵列在第二可编程布线组和功能块输入布线组的交叉点处将可编程布线组彼此连接，和/或第五开关元件 阵列，其在第二可编程布线组和功能块输出布线的分支线的交叉点处将可编程布线组彼此连接。

公开(公告)号：US08843795B2

公开(公告)日：2014-09-23

申请号：US12282482

申请日：2007-03-01

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318516

摘要： A reconfigurable device test scheme is provided for making a test of a reconfigurable device with configuration data which is loaded a smaller number of times. A reconfigurable device used herein holds a plurality of configuration data and is capable of instantaneously switching which configuration is implemented thereby. Specifically, one transfer configuration data and one or more test configuration data are previously loaded in a configuration memory of the reconfigurable device, and a test is made while sequentially switching the transfer configuration data and the test configuration data. In this way, the same configuration data need not be reloaded over and over, so that the test can be made with a smaller number of times of loading as compared with before.

摘要翻译： 提供了可重构设备测试方案，用于对可重新配置设备进行测试，配置数据加载次数较少。 这里使用的可重构装置保持多个配置数据，并且能够即时切换由此实现的配置。 具体而言，将一个传输配置数据和一个或多个测试配置数据预先加载到可重构设备的配置存储器中，并且在顺序切换传送配置数据和测试配置数据的同时进行测试。 这样，相同的配置数据不需要一次又一次地重新加载，因此与以前相比，能够以较少的加载次数进行测试。

公开(公告)号：US08640071B2

公开(公告)日：2014-01-28

申请号：US12995598

申请日：2009-05-15

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A circuit design system 10 includes storage means 11 to store structure description information 11a of a reconfigurable circuit including an array of cells 1 including a plurality of switches 2, and application circuit netlist information 11b used to specify an application, circuit generation unit 12a to generate structure description information 11a based on the structure description information 11a and the application circuit netlist information 11b stored in the storage means 11, and circuit evaluation unit 12b to evaluate the structure description information 11a generated by the circuit generation unit 12a, wherein the circuit generation unit 12a generates the structure description information 11a by deleting at least one of the switches 2 from the structure description information 11a based on an evaluation result obtained by the circuit evaluation unit 12b.

摘要翻译： 电路设计系统10包括存储装置11，用于存储包括包括多个开关2的单元阵列1的可重新配置电路的结构描述信息11a，以及用于指定应用的应用电路网表信息11b，生成电路生成单元12a 基于存储在存储装置11中的结构描述信息11a和应用电路网表信息11b的结构描述信息11a和用于评估由电路生成单元12a生成的结构描述信息11a的电路评估单元12b，其中电路生成单元 12a通过根据由电路评估单元12b获得的评估结果从结构描述信息11a中删除开关2中的至少一个来生成结构描述信息11a。

公开(公告)号：US08390321B2

公开(公告)日：2013-03-05

申请号：US13138643

申请日：2010-02-19

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  G06F7/575 ,  H03K19/17728

摘要： Provided is a reconfigurable logic circuit that can effectively use a preposition logic that composes a logic block. The reconfigurable logic block according to the present invention includes a plurality of logic blocks (199) having a full adder (30), two preposition logics (20) that perform a plurality of logic operations according to configuration data, an extended logic block (60) that can perform the logic operation of one or more kinds. Outputs (21A and 21B) of the preposition logic are respectively connected to two argument inputs (A and B) of the full adder (30). A carry output (CO) of the full adder (30) is connected to the extended logic block (60). One selected from a plurality of signals including a fixed logic value is input to a carry input (CI) of the full adder according to the configuration data, and the extended logic block of other logic block generates an output signal according to an output of the extended logic block.

摘要翻译： 提供了可以有效地使用构成逻辑块的介词逻辑的可重构逻辑电路。 根据本发明的可重构逻辑块包括具有全加器（30）的多个逻辑块（199），根据配置数据执行多个逻辑运算的两个介词逻辑（20），扩展逻辑块（60 ），可以执行一种或多种逻辑运算。 前置逻辑的输出（21A和21B）分别连接到全加器（30）的两个自变量输入（A和B）。 全加器（30）的进位输出（CO）连接到扩展逻辑块（60）。 从包括固定逻辑值的多个信号中选择的一个根据配置数据输入到全加器的进位输入（CI），并且其它逻辑块的扩展逻辑块根据输出信号产生输出信号 扩展逻辑块。

公开(公告)号：US08189365B2

公开(公告)日：2012-05-29

申请号：US12742018

申请日：2008-09-09

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： H01L27/101 ,  B82Y10/00 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/17 ,  G11C2213/53 ,  G11C2213/75 ,  H01L27/24 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778

摘要： A plurality of three-terminal variable resistance switching elements each having a source electrode, a drain electrode, and a gate electrode are connected to each other in series. The source electrode of each of the three-terminal variable resistance switching elements and the drain electrode of its adjacent three-terminal variable resistance switching element are connected to each other through a wiring segment to form a lane. A potential holding section for holding a predetermined potential level is connected to the wiring segment. A column group is configured by selecting one of the three-terminal variable resistance elements in each lane. A common gate line is connected to each of the gate electrodes of the three-terminal variable resistance elements belonging to the column group.

摘要翻译： 多个具有源电极，漏电极和栅电极的三端可变电阻开关元件彼此串联连接。 三端可变电阻开关元件中的每一个的源电极和其相邻的三端可变电阻开关元件的漏电极通过布线段彼此连接以形成通道。 用于保持预定电位电平的电位保持部分连接到布线段。 通过选择每个通道中的三端可变电阻元件之一来配置列组。 公共栅极线连接到属于列组的三端可变电阻元件的每个栅电极。

公开(公告)号：US07919980B2

公开(公告)日：2011-04-05

申请号：US12526344

申请日：2008-02-29

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H01L25/00

CPC分类号： H03K19/17736 ,  H03K19/1778

摘要： A configurable circuit of the present invention includes a plurality of logic blocks (4), and a programmable bus which can program connections of plurality of logic blocks (4). The programmable bus includes a plurality of wires (11—x) arranged for each of signal transmission ranges corresponding to plurality of logic blocks (4), direct wire connection switch (711—x) which can program whether to directly connect or disconnect the wires between the adjacent signal transmission ranges, input selector (30—x) which can program a connection with any one of the plurality of wires, and programmable switch (40—x) which can program whether to make a connection with the wire corresponding to the adjacent signal transmission range for each of the plurality of wires. A plurality of programmable switches (40—x) are arranged for at least one of plurality of logic blocks (4).

摘要翻译： 本发明的可配置电路包括多个逻辑块（4）和可编程多个逻辑块（4）的连接的可编程总线。 可编程总线包括针对与多个逻辑块（4）相对应的每个信号传输范围布置的多条电线（11-x），直接电线连接开关（711-x），其可以编程是否直接连接或断开电线 在相邻的信号传输范围之间，可以编程与多个导线中的任一个的连接的输入选择器（30-x），以及可编程是否与对应于该导线的导线进行连接的可编程开关（40-x） 相邻的信号传输范围。 为多个逻辑块（4）中的至少一个布置多个可编程开关（40-x）。

公开(公告)号：US06362647B1

公开(公告)日：2002-03-26

申请号：US09413693

申请日：1999-10-07

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K19177

CPC分类号： H03K19/17776 ,  G11C7/20 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/1778

摘要： A circuit for writing data to configuration memories is utilized to write initial value data to the configuration memories, thereby initializing the same. In addition, a transistor for providing disconnection between a writing data signal and an output signal of a configuration memory is inserted so that no collision occurs between both signals during the writing of data to the configuration memory.

摘要翻译： 用于将数据写入配置存储器的电路用于将初始值数据写入配置存储器，从而初始化它们。 此外，插入用于提供写入数据信号和配置存储器的输出信号之间的断开的晶体管，使得在向配置存储器写入数据期间两个信号之间不发生冲突。