公开(公告)号：US20200020789A1

公开(公告)日：2020-01-16

申请号：US16576370

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20170338330A1

公开(公告)日：2017-11-23

申请号：US15494499

申请日：2017-04-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

CPC classification number: H01L29/66825 ,  H01L21/32133 ,  H01L27/11521 ,  H01L29/42328

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US12144172B2

公开(公告)日：2024-11-12

申请号：US17745639

申请日：2022-05-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Zhuoqiang Jia ,  Leo Xing ,  Xian Liu ,  Serguei Jourba ,  Nhan Do

IPC: H10B41/49 ,  H01L21/28 ,  H01L29/66 ,  H10B41/35 ,  H10B41/41 ,  H01L29/423

Abstract: A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material. Then, memory cells are formed in the first area, HV devices in the second area and logic devices in the third area.

公开(公告)号：US11799005B2

公开(公告)日：2023-10-24

申请号：US17346524

申请日：2021-06-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  Chunming Wang ,  Xian Liu ,  Nhan Do ,  Guo Xiang Song

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate. The conductive spacer includes a lower surface that faces and matches the shape of the reshaped upper surface.

公开(公告)号：US20230262975A1

公开(公告)日：2023-08-17

申请号：US17745639

申请日：2022-05-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Zhuoqiang Jia ,  Leo Xing ,  Xian Liu ,  Serguei Jourba ,  Nhan Do

IPC: H01L27/11546 ,  H01L27/11524 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11529

CPC classification number: H01L27/11546 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/66825 ,  H01L27/11529 ,  H01L29/42328

Abstract: A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material. Then, memory cells are formed in the first area, HV devices in the second area and logic devices in the third area.

公开(公告)号：US11621335B2

公开(公告)日：2023-04-04

申请号：US17701840

申请日：2022-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: G11C11/34 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04

Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.

公开(公告)号：US11508442B2

公开(公告)日：2022-11-22

申请号：US17074103

申请日：2020-10-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  Chunming Wang ,  Xian Liu ,  Nhan Do ,  Guangming Lin ,  Yaohua Zhu

IPC: G11C16/12 ,  G11C16/26 ,  G11C16/14

Abstract: The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

公开(公告)号：US20220293756A1

公开(公告)日：2022-09-15

申请号：US17346524

申请日：2021-06-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  CHUNMING WANG ,  XIAN LIU ,  NHAN DO ,  GUO XIANG SONG

IPC: H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate. The conductive spacer includes a lower surface that faces and matches the shape of the reshaped upper surface.

公开(公告)号：US20220278119A1

公开(公告)日：2022-09-01

申请号：US17339880

申请日：2021-06-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Guo Xiang Song ,  Chunming Wang ,  Leo Xing ,  Xian Liu ,  Nhan Do

IPC: H01L27/11529

Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.

公开(公告)号：US20220216316A1

公开(公告)日：2022-07-07

申请号：US17701840

申请日：2022-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: H01L29/423 ,  H01L29/66 ,  G11C16/04 ,  H01L29/788

Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.