公开(公告)号：US09378834B2

公开(公告)日：2016-06-28

申请号：US14486673

申请日：2014-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Yao Zhou ,  Bin Sheng ,  Jiaxu Peng ,  Yaohua Zhu

IPC: G11C16/06 ,  G11C16/24 ,  G11C29/02 ,  G11C29/28 ,  G11C16/28 ,  G11C29/12

CPC classification number: G11C16/24 ,  G11C5/145 ,  G11C5/147 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/028 ,  G11C29/28 ,  G11C2029/1204

Abstract: A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.

Abstract translation: 公开了一种用于高速闪存系统的位线调节器。 位线调节器响应于通过将位线的偏置电压与参考电压进行比较而产生的一组修整位。

公开(公告)号：US11508442B2

公开(公告)日：2022-11-22

申请号：US17074103

申请日：2020-10-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  Chunming Wang ,  Xian Liu ,  Nhan Do ,  Guangming Lin ,  Yaohua Zhu

IPC: G11C16/12 ,  G11C16/26 ,  G11C16/14

Abstract: The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

公开(公告)号：US09997252B2

公开(公告)日：2018-06-12

申请号：US15706586

申请日：2017-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiao Yan Pi ,  Xiaozhou Qian ,  Kai Man Yue ,  Yao Zhou ,  Yaohua Zhu

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/08 ,  G11C7/14 ,  G11C16/24 ,  G11C7/06 ,  G11C29/02 ,  G11C7/12 ,  G11C29/12 ,  G11C29/50

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C16/08 ,  G11C16/24 ,  G11C29/025 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

公开(公告)号：US20160027519A1

公开(公告)日：2016-01-28

申请号：US14486673

申请日：2014-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Yao Zhou ,  Bin Sheng ,  Jiaxu Peng ,  Yaohua Zhu

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C5/145 ,  G11C5/147 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/028 ,  G11C29/28 ,  G11C2029/1204

Abstract: A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.

Abstract translation: 公开了一种用于高速闪存系统的位线调节器。 位线调节器响应于通过将位线的偏置电压与参考电压进行比较而产生的一组修整位。

公开(公告)号：US11798644B2

公开(公告)日：2023-10-24

申请号：US17669793

申请日：2022-02-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Yaohua Zhu

IPC: G11C7/00 ,  G11C29/04 ,  G11C8/10

CPC classification number: G11C29/04 ,  G11C8/10

Abstract: Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.

公开(公告)号：US20180005701A1

公开(公告)日：2018-01-04

申请号：US15706586

申请日：2017-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiao Yan Pi ,  Xiaozhou Qian ,  Kai Man Yue ,  Yao Zhou ,  Yaohua Zhu

IPC: G11C16/28 ,  G11C7/12 ,  G11C29/02 ,  G11C16/08 ,  G11C7/14 ,  G11C16/24 ,  G11C7/06 ,  G11C29/50 ,  G11C29/12

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C16/08 ,  G11C16/24 ,  G11C29/025 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.