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公开(公告)号：US6065114A
公开(公告)日：2000-05-16
申请号：US64091
申请日：1998-04-21
申请人： Achmed Rumi Zahir , Jonathan K. Ross , Carol Thompson , Cary Coutant , Prasad Raje , Sunil Saxena
发明人： Achmed Rumi Zahir , Jonathan K. Ross , Carol Thompson , Cary Coutant , Prasad Raje , Sunil Saxena
CPC分类号： G06F9/4812 , G06F9/3009 , G06F9/30127 , G06F9/30134 , G06F9/4425 , G06F9/461
摘要： A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area. On return from interruption, if IFM is validated, CFM is restored from IFM else CFM remains unchanged. The COVER instruction enables lightweight interrupt handling in a processor with a Register Stack.
摘要翻译： 提供了一种在处理器中切换上下文的计算机实现的方法。 处理器包括具有第一和第二部分的寄存器堆栈（RS）。 该处理器包括一个寄存器堆栈引擎（RSE），用于在第二部分和存储区域之间以指令执行相关和独立模式之一交换信息。 计算机实现的切换上下文的方法包括以下步骤：确定是否发生中断; 配置为存储第二寄存器（CFM）的内容的第一寄存器（IFM）无效，所述CFM被配置为存储与所述第一部分相关的控制信息; 确定中断处理程序是否需要访问RS; 如果是，则IFM被验证，CFM的内容被复制到IFM，并且使RSE在RS的第一和第二部分与存储区域之间交换信息。 从中断返回时，如果IFM被验证，则从IFM恢复CFM，否则CFM保持不变。 COVER指令在具有寄存器堆栈的处理器中实现轻量级中断处理。
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公开(公告)号：US07765238B2
公开(公告)日：2010-07-27
申请号：US11799429
申请日：2007-04-30
CPC分类号： G06F17/3033 , G06F12/1018
摘要： A method for mapping an active entry within a virtually hashed page table is disclosed. An active entry within a virtually hashed page table is populated. A link table for locating a link at an offset from an active entry is maintained. This link table continues to be maintained as a valid link table until an occupied head bucket threshold is exceeded or a collision has occurred.
摘要翻译： 公开了一种在虚拟散列页表内映射活动条目的方法。 虚拟散列页表中的活动条目将被填充。 用于定位与活动条目偏移的链接的链接表保持不变。 该链接表继续维持为有效的链接表，直到超过占用的头桶阈值或发生了冲突。
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公开(公告)号：US07421689B2
公开(公告)日：2008-09-02
申请号：US10695267
申请日：2003-10-28
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译： 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。
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24.发明授权公开(公告)号：US07340630B2
公开(公告)日：2008-03-04
申请号：US10638696
申请日：2003-08-08
申请人： Dale C. Morris , Jonathan K. Ross
发明人： Dale C. Morris , Jonathan K. Ross
CPC分类号： G06F1/14 , H04J3/0638
摘要： A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicating the time of transmission according to the local clock) to the other (“slave”) processors. Each slave processor responds by returning a “response” time stamp (indicating the time of transmission of the response according to the local slave clock) of its own along with the received request time stamp. The master calculates clock adjustment values from the time of receipt of the responses and the included time stamps. This allows asynchronous clocks to be synchronized so that application time stamps can be validly compared across processors.
摘要翻译： 多处理器计算机系统包括多个数据处理器，每个数据处理器具有用于向应用软件提供时间戳的内部时钟。 处理器轮流作为同步主机。 本主机向另一个（“从”）处理器发送“请求”时间戳（指示根据本地时钟发送的时间）。 每个从属处理器通过根据接收到的请求时间戳返回一个“响应”时间戳（指示根据本地从属时钟发送响应的时间）。 主人从接收到响应时间和包含的时间戳计算时钟调整值。 这允许异步时钟被同步，以便可以在处理器之间有效地比较应用程序时间戳。
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公开(公告)号：US07334112B2
公开(公告)日：2008-02-19
申请号：US10702355
申请日：2003-11-06
IPC分类号： G06F9/312
CPC分类号： G06F9/30123 , G06F9/30134 , G06F9/384 , G06F9/3842 , G06F9/3861
摘要： Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault. The instruction execution unit executes the instruction is the instruction execution unit determines that the register is within the current register stack frame. When execution of the instruction requires reading from a register referenced by the instruction, the instruction execution unit executes the instruction whether or not the register referenced by the instruction is within the current register stack frame.
摘要翻译： 公开了用于管理对当前寄存器堆栈帧之外的寄存器的访问的方法和装置。 处理器中的指令执行单元接收要执行的指令。 处理器包括寄存器堆栈，寄存器堆栈包括多个寄存器堆栈帧。 每个寄存器堆栈帧包括零个或多个寄存器。 多个寄存器堆栈帧中的一个是当前寄存器堆栈帧。 当执行指令需要写入由指令引用的寄存器时，指令执行单元确定该指令引用的寄存器是否在当前寄存器堆栈帧内。 如果指令执行单元确定寄存器不在当前寄存器堆栈帧内，则指令执行单元不执行指令，并且例如可能产生故障。 指令执行单元执行指令是指令执行单元确定寄存器在当前寄存器堆栈帧内。 当指令的执行需要从指令引用的寄存器读取时，指令执行单元执行指令，该指令是否由指令引用的寄存器是否在当前寄存器堆栈帧内。
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26.发明授权Method and apparatus for performing critical tasks using speculative operations 失效使用投机操作执行关键任务的方法和装置公开(公告)号：US06941449B2
公开(公告)日：2005-09-06
申请号：US10092093
申请日：2002-03-04
申请人： Jonathan K. Ross
发明人： Jonathan K. Ross
CPC分类号： G06F9/3865 , G06F9/383 , G06F9/3842
摘要： Method and apparatus for performing a critical task using a load that is speculative. Specifically, a method of computation for performing critical tasks with speculative operations is described in one embodiment. The critical task is performed to achieve a first result while a condition of a processor used to perform said critical task is unknown. In parallel, the condition of the processor is determined. If the condition is as expected, then the first result is committed. If the condition is not as expected, then the condition is fixed to be as expected. The first result benignly fails. Also, the critical task is re-performed using the operation that is speculative resulting in a second result. The second result is then committed.
摘要翻译： 使用推测的负载执行关键任务的方法和装置。 具体地，在一个实施例中描述了用推测操作执行关键任务的计算方法。 执行关键任务以在用于执行所述关键任务的处理器的条件是未知的情况下实现第一结果。 并行地确定处理器的状况。 如果条件符合预期，则第一个结果将被提交。 如果条件不符合预期，则条件固定为预期。 第一个结果是良性的失败。 此外，使用推测的操作导致第二个结果重新执行关键任务。 然后第二个结果被提交。
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27.发明授权Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loads 失效使用动态延迟操作信息来控制控制推测负载的急速推迟的方法和系统公开(公告)号：US06931515B2
公开(公告)日：2005-08-16
申请号：US10208095
申请日：2002-07-29
申请人： Jonathan K. Ross , Dale Morris
发明人： Jonathan K. Ross , Dale Morris
CPC分类号： G06F9/3865 , G06F9/383 , G06F9/3842
摘要： A method and system for determining, at run-time, whether or not to defer an exception that arises during execution of a control-speculative load instruction based on a recent history of execution of that control-speculative load instruction. The method and system relies on recent execution history stored in a speculative-load-accelerated-deferral table. If an exception arises during execution of a control-speculative load instruction, then the speculative-load-accelerated-deferral table is searched for an entry corresponding to the control-speculative load instruction. If an entry is found, then the exception is deferred, since the speculative-load-accelerated-deferral table indicates that a recent exception arising from execution of the control-speculative load instruction was not recovered via a chk.s-mediated branch to a recovery block, and not otherwise used by a non-speculative instruction. By contrast, if no entry corresponding to the control-speculative load instruction is found in the speculative-load-accelerated-deferral table, then the exception is immediately handled.
摘要翻译： 一种方法和系统，用于在运行时确定是否推迟在执行控制推测加载指令期间出现的异常，这是基于该控制推测加载指令的执行的最近历史。 该方法和系统依赖于存储在推测加载延迟表中的最近执行历史。 如果在执行控制推测加载指令期间出现异常，则搜索推测加载加速延迟表以查找与控制推测加载指令相对应的条目。 如果找到条目，则异常被延迟，因为推测加载加速延迟表指示由控制推测加载指令的执行引起的最近异常没有通过chk.s介入的分支恢复到 恢复块，而不是由非推测性指令使用。 相反，如果在推测加载延迟表中没有找到与控制推测加载指令相对应的条目，则立即处理异常。
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28.发明授权System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor's execution of instructions during a state saving context switch 失效用于在状态保存上下文切换期间同步寄存器堆栈引擎（RSE）和备份存储器映像与处理器执行指令的系统和方法公开(公告)号：US06367005B1
公开(公告)日：2002-04-02
申请号：US09677617
申请日：2000-10-02
IPC分类号： G06F948
CPC分类号： G06F9/30127 , G06F9/3004 , G06F9/30043 , G06F9/30134 , G06F9/4484
摘要： A computer implemented method in a processor to perform a backing store switch from a first context (source context) to a second context (target context) is provided whereby the backing store memory image and RSE will be synchronized with the processor's execution of instructions. The processor includes a register stack (RS) device that includes a portion allocated for dirty registers. The portion is defined by first and second physical register numbers. The processor further includes a register stack engine (RSE) to exchange information in one of an instruction execution dependent and independent modes between a storage area and the RS. The processor further includes a FLUSHRS state machine to notify the RSE to store dirty register in the RS to a backing store located in a memory.
摘要翻译： 提供了一种用于执行从第一上下文（源上下文）到第二上下文（目标上下文）的后备存储切换的处理器中的计算机实现的方法，由此后备存储存储器映像和RSE将与处理器的指令执行同步。 处理器包括寄存器堆栈（RS）设备，其包括分配给脏寄存器的部分。 该部分由第一和第二物理寄存器编号定义。 该处理器还包括一个寄存器堆栈引擎（RSE），用于以存储区域和RS之间的指令执行依赖和独立模式之一交换信息。 处理器还包括FLUSHRS状态机，以通知RSE将RS中的脏寄存器存储到位于存储器中的后备存储器。
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公开(公告)号：US6115777A
公开(公告)日：2000-09-05
申请号：US63739
申请日：1998-04-21
CPC分类号： G06F9/4812 , G06F13/24 , G06F9/3009 , G06F9/30134 , G06F9/3861 , G06F9/461
摘要： A method for returning from an interrupting context to an interrupted context in a processor is disclosed. The processor executes a programmed flow of instructions. The processor includes a register stack (RS) and a register stack engine (RSE) to exchange information between the RS and the storage area. The method includes the following steps: (a.) A first pointer (PTR) is generated. The pointer (PTR) points to a location in the storage area where dirty registers (previously unsaved) of an interrupted context are stored; (b.) It is determined whether a mathematical relation is valid between the first pointer and the second pointer (BSPLOAD) to a location in the storage area from where the RSE is configured to load dirty register values into the RS; (c) The second pointer is caused to point to a next location in the storage area if the relation is valid; and (d) A register of the RS is loaded with a content of the next location in the storage area until the mathematical relation becomes invalid.
摘要翻译： 公开了一种用于在处理器中从中断上下文返回到中断的上下文的方法。 处理器执行编程的指令流程。 处理器包括寄存器堆栈（RS）和寄存器堆栈引擎（RSE），以在RS和存储区域之间交换信息。 该方法包括以下步骤：（a。）生成第一个指针（PTR）。 指针（PTR）指向存储区域中存在中断上下文的脏寄存器（以前未保存）的位置; （b。）确定第一指针和第二指针（BSPLOAD）之间的数学关系是否与存储区域中的RSE被配置为将脏寄存器值加载到RS中的位置有关; （c）如果关系有效，第二个指针指向存储区域中的下一个位置; 和（d）RS的寄存器被加载在存储区域中的下一个位置的内容，直到数学关系变得无效。
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