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21.发明授权公开(公告)号：US07320938B2
公开(公告)日：2008-01-22
申请号：US11460671
申请日：2006-07-28
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.
摘要翻译： 用于减少半导体器件的自对准硅化物工艺中的枝晶形成的方法包括在半导体衬底上形成硅化物金属层，所述半导体器件具有一个或多个扩散区域，一个或多个隔离区域和一个或多个栅极结构 形成在其上。 金属层的富金属部分的浓度通过向其中引入硅而降低，半导体器件退火。
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22.发明授权公开(公告)号：US07109116B1
公开(公告)日：2006-09-19
申请号：US11161064
申请日：2005-07-21
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.
摘要翻译： 用于减少半导体器件的自对准硅化物工艺中的枝晶形成的方法包括在半导体衬底上形成硅化物金属层，所述半导体器件具有一个或多个扩散区域，一个或多个隔离区域和一个或多个栅极结构 形成在其上。 金属层的富金属部分的浓度通过向其中引入硅而降低，半导体器件退火。
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公开(公告)号：US06509265B1
公开(公告)日：2003-01-21
申请号：US09666240
申请日：2000-09-21
申请人： Patrick W. DeHaven , Anthony G. Domenicucci , Lynne M. Gignac , Glen L. Miles , Prabhat Tiwari , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
发明人： Patrick W. DeHaven , Anthony G. Domenicucci , Lynne M. Gignac , Glen L. Miles , Prabhat Tiwari , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/76855 , H01L21/76856 , H01L21/76864
摘要： A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.
摘要翻译： 一种用于形成具有平坦界面的导电触头的工艺。 将含有铌和钛的层沉积在硅衬底上，所得结构在约500℃至约700℃的含氮气氛中退火。通过该过程，硅化物和硅之间的平坦界面是 在退火时形成不太可能导致结漏电。 退火步骤还产生更均匀的双层，这是在随后的钨沉积期间防止钨侵蚀的更好的屏障。 还形成更大的硅化物晶粒，使得产生更少的晶界，减少晶界中的金属扩散。 该过程可用于形成非常小的器件和浅结的接触，例如当前和未来的半导体器件所需要的。
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公开(公告)号：US08368070B2
公开(公告)日：2013-02-05
申请号：US13360277
申请日：2012-01-27
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.
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公开(公告)号：US20120126366A1
公开(公告)日：2012-05-24
申请号：US13360270
申请日：2012-01-27
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.
摘要翻译： 反熔丝结构和在反熔丝结构内形成接触的方法。 反熔丝结构包括具有上覆金属层的基板，形成在金属层的上表面上的电介质层，以及由通过电介质层蚀刻到金属层中的接触孔内的接触材料形成的接触。 接触通孔在接触通孔的底表面处包括金属材料，并且在金属材料的顶部上包括未处理或部分处理的金属前体。
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公开(公告)号：US06417567B1
公开(公告)日：2002-07-09
申请号：US09482547
申请日：2000-01-13
申请人： Anthony G. Domenicucci , Lynne M. Gignac , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong , Roy A. Carruthers , Christian Lavoie , John A. Miller
发明人： Anthony G. Domenicucci , Lynne M. Gignac , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong , Roy A. Carruthers , Christian Lavoie , John A. Miller
IPC分类号： H01L2348
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/28568 , H01L21/3212 , H01L21/76856 , H01L2221/1078
摘要： A conductive contact having an atomically flat interface. The contact includes, in order, a silicon substrate, a highly disordered silicide layer, and a titanium oxynitride layer. The silicide layer is formed of titanium, silicon, and one of the elements tungsten, tantalum, and molybdenum. The interface between the silicon substrate and the silicide layer is atomically flat. The flat interface prevents diffusion of conductive materials into the underlying silicon substrate. The contact is useful especially for very small devices and shallow junctions, such as are required for ULSI shallow junctions.
摘要翻译： 具有原子平坦界面的导电接触。 接触依次包括硅衬底，高度无序的硅化物层和氮氧化钛层。 硅化物层由钛，硅和元素钨，钽和钼之一形成。 硅衬底和硅化物层之间的界面是原子平坦的。 平面界面防止导电材料扩散到下面的硅衬底中。 该接触对于非常小的器件和浅接头是有用的，例如ULSI浅结点所需的。
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27.发明授权Capping layer for improved silicide formation in narrow semiconductor structures 失效用于改善窄半导体结构中硅化物形成的封盖层公开(公告)号：US06388327B1
公开(公告)日：2002-05-14
申请号：US09756938
申请日：2001-01-09
申请人： Kenneth J. Giewont , Stephen Bruce Brodsky , Cyril Cabral, Jr. , Anthony G. Domenicucci , Craig Mitchell Ransom , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
发明人： Kenneth J. Giewont , Stephen Bruce Brodsky , Cyril Cabral, Jr. , Anthony G. Domenicucci , Craig Mitchell Ransom , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
IPC分类号： H01L2348
CPC分类号： C23C14/0094 , C23C14/0641 , H01L21/28052 , H01L21/28518 , H01L21/2855
摘要： A capping layer for a semiconductor structure is described. The capping layer is deposited over a silicide-forming metal and has a composition such that nitrogen diffusion therefrom is insufficient to cause formation of an oxynitride from an oxide layer on the underlying silicon. The capping layer may be a metal layer from which no N diffusion occurs, or one or more layers including Ti and/or TiN arranged so that N atoms do not reach the oxide layer. A method is also described for forming the Ti and TiN layers. It is advantageous to deposit non-stoichiometric TiN deficient in N, by sputtering from a Ti target in a nitrogen flow insufficient to cause formation of a nitride on the target.
摘要翻译： 描述了半导体结构的覆盖层。 覆盖层沉积在硅化物形成金属上，并且具有使得其中的氮扩散不足以引起下层硅上的氧化物层形成氧氮化物的组成。 覆盖层可以是不发生N扩散的金属层，或者包括Ti和/或TiN的一个或多个层，以使得N原子不到达氧化物层。 还描述了形成Ti和TiN层的方法。 通过在不足以引起目标上形成氮化物的氮气流中从Ti靶溅射而在N中沉积非化学计量的TiN是有利的。
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公开(公告)号：US06387790B1
公开(公告)日：2002-05-14
申请号：US09602228
申请日：2000-06-23
申请人： Anthony Gene Domenicucci , Chung-Ping Eng , William Joseph Murphy , Tina J. Wagner , Yun-Yu Wang , Kwong Hon Wong
发明人： Anthony Gene Domenicucci , Chung-Ping Eng , William Joseph Murphy , Tina J. Wagner , Yun-Yu Wang , Kwong Hon Wong
IPC分类号： H01L213205
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76864
摘要： A method of fabricating a Ti-containing liner having good contact resistance and coverage of a contact hole is provided. The method which converts an amorphous region of ionized metal plasma deposited Ti into a substantially crystalline region includes (a) providing a structure having at least one contact hole formed therein, said at least one contact hole exposing at least a portion of a cobalt disilicide contact formed in a semiconductor substrate; (b) depositing a Ti/TiN liner in said at least one contact hole by ionized metal plasma deposition; (c) annealing said Ti/TiN liner under conditions effective to recrystallize any amorphous region formed during said annealing into a crystalline region including a TiSi2 top layer and a CoSix bottom layer; and (d) optionally forming a conductive material on said Ti/TiN liner.
摘要翻译： 提供一种制造具有良好接触电阻和接触孔覆盖度的含Ti衬垫的方法。 将电离金属等离子体沉积的Ti的非晶区域转化成基本上结晶的区域的方法包括（a）提供其中形成有至少一个接触孔的结构，所述至少一个接触孔暴露至少一部分二硅化钴接触 形成在半导体衬底中; （b）通过电离金属等离子体沉积在所述至少一个接触孔中沉积Ti / TiN衬垫; （c）在有效使所述退火过程中形成的任何非晶区域再结晶成包括TiSi 2顶层和CoSix底层的结晶区域的条件下退火所述Ti / TiN衬垫; 和（d）任选地在所述Ti / TiN衬垫上形成导电材料。
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29.发明授权Method of TEM sample preparation for electron holography for semiconductor devices 失效半导体器件电子全息术的TEM样品制备方法公开(公告)号：US07560692B2
公开(公告)日：2009-07-14
申请号：US11617386
申请日：2006-12-28
CPC分类号： G01N1/2806
摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.
摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。
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30.发明授权Transmission electron microscopy sample preparation method for electron holography 失效透射电子显微镜用于电子全息术的样品制备方法公开(公告)号：US07214935B2
公开(公告)日：2007-05-08
申请号：US10711690
申请日：2004-09-30
申请人： Thomas A. Bauer , Steven H. Boettcher , Anthony G. Domenicucci , John G. Gaudiello , Leon J. Kimball , Jeffrey S. McMurray , Yun-Yu Wang
发明人： Thomas A. Bauer , Steven H. Boettcher , Anthony G. Domenicucci , John G. Gaudiello , Leon J. Kimball , Jeffrey S. McMurray , Yun-Yu Wang
CPC分类号： G01N1/32 , G01N23/04 , H01J2237/2614
摘要： A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.
摘要翻译： 制备用于电子全息术的透射电子显微镜（TEM）样品的方法包括在样品上的感兴趣区域上形成牺牲材料，并将样品抛光至所需厚度，其中在抛光过程中保护感兴趣区域免于四舍五入 。 抛光后，从样品中除去牺牲材料。
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