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公开(公告)号：US07467177B2
公开(公告)日：2008-12-16
申请号：US11019853
申请日：2004-12-21
IPC分类号： G06F7/38
CPC分类号： G06F7/49963
摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.
摘要翻译： 描述了执行灵活舍入方案的数学电路。 这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。 在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选择的舍入常数，计算校正因子，并将舍入常数，校正因子和 一个数据项以获得舍入的数据项。
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公开(公告)号：US07242633B1
公开(公告)日：2007-07-10
申请号：US11044740
申请日：2005-01-26
申请人： Alvin Y. Ching , Raymond C. Pang , Steven P. Young , Thanh Pham
发明人： Alvin Y. Ching , Raymond C. Pang , Steven P. Young , Thanh Pham
IPC分类号： G11C8/00
CPC分类号： H03K19/1776 , G11C7/1075 , G11C8/10 , G11C8/16 , G11C11/412 , G11C11/413 , G11C15/00
摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.
摘要翻译： 根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。 电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。 第二端口具有读逻辑电路和写逻辑电路。 第二输出耦合到第二端口，并且还从存储器产生数据。 公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。 最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。 此外，公开了一种访问存储器中的数据的方法。
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公开(公告)号：US07567997B2
公开(公告)日：2009-07-28
申请号：US11019518
申请日：2004-12-21
IPC分类号： G06F7/48
CPC分类号： G06F7/5443
摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
摘要翻译： 在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。 该IC允许实现一些基本的数学函数，例如加，减，乘和除。 可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。
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公开(公告)号：US09002915B1
公开(公告)日：2015-04-07
申请号：US12417048
申请日：2009-04-02
申请人： Steven P. Young , Brian C. Gaide
发明人： Steven P. Young , Brian C. Gaide
CPC分类号： G06F5/015 , H03K19/17736
摘要： A circuit for shifting bussed data includes a first column of shift blocks, a compare block, and a second column of multiplexer blocks. The first column shifts the bussed data by a number of bits specified by first bits of a shift control input. The compare block determines the value of a second bit of the shift control input and creates an output reflecting that value. The second column has a control input coupled to the output of the compare block, shifts the data by one byte when the second bit of the shift control input has a first value, and does not shift the data when the second bit has a second value. The shift, compare, and multiplexer blocks can be substantially similar logic blocks programmable to perform any of these functions, can include N-bit data inputs and outputs, and can operate on the bussed data as an N-bit bus.
摘要翻译： 用于移位总线数据的电路包括第一列移位块，比较块和第二列复用器块。 第一列将总线数据移位由移位控制输入的第一位指定的位数。 比较块确定移位控制输入的第二位的值，并创建反映该值的输出。 第二列具有耦合到比较块的输出的控制输入，当移位控制输入的第二位具有第一值时将数据移位一个字节，并且当第二位具有第二值时不移位数据 。 移位，比较和多路复用器块可以是基本相似的可编程以执行这些功能的逻辑块，可以包括N位数据输入和输出，并且可以作为N位总线对总线数据进行操作。
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公开(公告)号：US08058905B1
公开(公告)日：2011-11-15
申请号：US12363722
申请日：2009-01-31
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.
摘要翻译： 描述了便于在诸如现场可编程门阵列（FPGA）的可编程集成电路中分配门控时钟的电路和方法。 通过在分层时钟分配网络中的不同位置提供门控时钟驱动器电路，可以在FPGA中实现动态功耗。 门控时钟电路通过使能信号为时钟元件提供门控时钟信号。 包括时钟元件和可编程互连瓦片的可配置逻辑块（CLB）设置在门阵列中。 时钟信号通过时钟分配网络分发给CLB。 对应于一些时钟信号提供时钟使能信号。 在时钟分配网络中提供时钟缓冲器或驱动器，将门控时钟信号驱动到CLB。 通过在FPGA的部分不活动时使用本发明的一个或多个实施例来禁用某些时钟元件，动态功耗降低。
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26.发明授权Methods and apparatus for device-specific configuration of a programmable integrated circuit 有权可编程集成电路器件特定配置的方法和装置公开(公告)号：US07902863B1
公开(公告)日：2011-03-08
申请号：US12049189
申请日：2008-03-14
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , G06F17/5054
摘要： Methods and apparatus for configuring a programmable integrated circuit are described. In one example, a configuration stream having first data for programming first locations in a configuration memory and an instruction for referencing circuitry in the programmable integrated circuit is received. Second data is obtained from the circuitry based on the instruction. Second locations in the configuration memory are programmed in response to the second data.
摘要翻译： 描述用于配置可编程集成电路的方法和装置。 在一个示例中，接收具有用于对配置存储器中的第一位置进行编程的第一数据和用于参考可编程集成电路中的电路的指令的配置流。 基于该指令的电路获得第二数据。 响应于第二数据对配置存储器中的第二位置进行编程。
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27.发明授权Error checking parity and syndrome of a block of data with relocated parity bits 有权错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验公开(公告)号：US07895509B1
公开(公告)日：2011-02-22
申请号：US12188935
申请日：2008-08-08
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译： 描述了用于错误检查信息的方法和装置。 配置数据包括数据位和奇偶校验位。 值得注意的是，可以重新定位奇偶校验位以确定校正子值。 通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。 识别配置数据的每个单词的位置。 确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。 存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。
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28.发明授权公开(公告)号：US07746106B1
公开(公告)日：2010-06-29
申请号：US12417040
申请日：2009-04-02
申请人： Brian C. Gaide , Steven P. Young
发明人： Brian C. Gaide , Steven P. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/1736 , H03K19/17728 , H03K19/17736
摘要： Circuits enabling feedback paths in a self-timed integrated circuit. Each of a plurality of interconnected logic blocks includes a logic circuit having first and second outputs, and means for placing, during an initial cycle, a self-timed first data signal on the second output onto a logic block output, and for placing, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs onto the logic block output. Initially, an output token is provided only when valid new data is received on the second output and on a select signal. Subsequently, the output token is provided only when either the first output of the logic circuit is selected, and valid new data is received on the first output and on the select signal; or the second output of the logic circuit is selected, and valid new data is received on the first and second outputs and on the select signal.
摘要翻译： 在自定时集成电路中实现反馈路径的电路。 多个相互连接的逻辑块中的每一个包括具有第一和第二输出的逻辑电路，以及用于在初始周期期间将第二输出上的自定时第一数据信号放置在逻辑块输出上并用于在 随后的周期中，在逻辑块输出上的第一或第二输出中的所选择的一个上的自定时第二数据信号。 最初，仅当在第二输出和选择信号上接收到有效的新数据时才提供输出令牌。 随后，仅当逻辑电路的第一输出被选择并且在第一输出和选择信号上接收到有效的新数据时才提供输出令牌; 或选择逻辑电路的第二输出，并在第一和第二输出和选择信号上接收有效的新数据。
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公开(公告)号：US07617472B1
公开(公告)日：2009-11-10
申请号：US12025637
申请日：2008-02-04
申请人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
发明人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , G06F2217/62
摘要： Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.
摘要翻译： 描述区域信号的信号分布。 集成电路包括全球信号分配网络，区域信号分配网络和区域缓冲器。 区域缓冲区具有耦合在区域信号分配网络末端的输出。 区域信号分配网络通过互连瓦片耦合到可配置的逻辑块。 区域缓冲器耦合到具有区域时钟的输入/输出块。 另外描述了用于区域信号分配的源同步接口。
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30.发明授权Characterizing circuit performance by separating device and interconnect impact on signal delay 有权通过分离器件和互连对信号延迟的影响来表征电路性能公开(公告)号：US07489152B2
公开(公告)日：2009-02-10
申请号：US11498371
申请日：2006-08-03
IPC分类号： G01R31/28
CPC分类号： G01R31/2882 , G01R31/318511 , G01R31/318516 , G01R31/3187
摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。
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