公开(公告)号：US06509739B1

公开(公告)日：2003-01-21

申请号：US09709184

申请日：2000-11-08

申请人： Martin L. Voogel ,  Leon Ly Nguyen ,  Narasimhan Vasudevan

发明人： Martin L. Voogel ,  Leon Ly Nguyen ,  Narasimhan Vasudevan

IPC分类号： G01R3128

CPC分类号： H01L22/34 ,  G01R31/026 ,  G01R31/316 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure provides defect information rapidly and accurately. The test structure includes a plurality of lines provided in a parallel orientation, a decoder coupled to the plurality of lines for selecting one of the plurality of lines, and a sense amplifier coupled to the selected line. To analyze an open, a line in the test structure is coupled to the sense amplifier. A high input signal is provided to the line. To determine the resistance of the open, a plurality of reference voltages are then provided to the sense amplifier. A mathematical model of the resistance of the line based on the reference voltage provided to the sense amplifier is generated. Using this mathematical model, the test structure can quickly detect and characterize defect levels down to a few parts-per-million at minimal expense.

摘要翻译： 测试结构快速准确地提供缺陷信息。 测试结构包括以平行取向提供的多条线，耦合到多条线的解码器，用于选择多条线中的一条线;以及读出放大器，耦合到所选择的线。 为了分析开路，测试结构中的一条线耦合到读出放大器。 线路上提供高输入信号。 为了确定开路的电阻，然后将多个参考电压提供给读出放大器。 产生基于提供给读出放大器的参考电压的线路的电阻的数学模型。 使用这种数学模型，测试结构可以以最小的成本快速检测和表征缺陷水平，达到百万分之几。

公开(公告)号：US5959821A

公开(公告)日：1999-09-28

申请号：US109479

申请日：1998-07-02

申请人： Martin L. Voogel

发明人： Martin L. Voogel

IPC分类号： H01L27/02 ,  H02H9/04 ,  H02H3/22

CPC分类号： H01L27/0251 ,  H02H9/046

摘要： An electrostatic discharge (ESD) protection circuit for an IC device including a triple-well SCR and a control circuit connected between the triple-well SCR and ground. The triple-well SCR is implemented using triple-well CMOS technology to facilitate connection of the control circuit by isolating both terminals of the triple-well SCR from ground. The control circuit includes a switch circuit, a capacitor, or a combination thereof, for controlling the holding voltage of the triple-well SCR. The switch circuit is closed during non-operation (i.e., before power is applied to the IC device protected by the SCR) so that electrostatic discharge (ESD) energy is transmitted to ground through the triple-well SCR. Similarly, the capacitor transmits ESD pulses to ground during ESD events. During normal operation of the IC device, the switch circuit is controlled by system voltage to remain open. In contrast, the capacitor is charged when a voltage pulse triggers the triple-well SCR during normal IC operation, thereby reliably switching off the triple-well SCR by decreasing the voltage across the SCR below the holding voltage.

摘要翻译： 一种用于IC器件的静电放电（ESD）保护电路，包括三阱SCR和连接在三阱SCR与地之间的控制电路。 使用三阱CMOS技术实现三阱SCR，以通过将三阱SCR的两个端子与地相隔离来促进控制电路的连接。 控制电路包括用于控制三阱SCR的保持电压的开关电路，电容器或其组合。 在非操作期间（即，在被SCR保护的IC器件被施加电力之前），开关电路闭合，使得静电放电（ESD）能量通过三阱SCR传输到地。 类似地，电容器在ESD事件期间将ESD脉冲发送到地。 在IC器件的正常工作期间，开关电路由系统电压控制以保持开路。 相比之下，当在正常IC操作期间电压脉冲触发三阱SCR时，电容器被充电，从而通过将SCR两端的电压降低到保持电压以下，从而可靠地关闭三阱SCR。

公开(公告)号：US5880620A

公开(公告)日：1999-03-09

申请号：US840582

申请日：1997-04-22

申请人： Daniel Gitlin ,  Sheau-Suey Li ,  Martin L. Voogel ,  Tiemin Zhao

发明人： Daniel Gitlin ,  Sheau-Suey Li ,  Martin L. Voogel ,  Tiemin Zhao

IPC分类号： G11C5/14 ,  H03K17/06 ,  H03K3/01

CPC分类号： G11C5/146 ,  H03K17/063 ,  H03K2217/0018

摘要： A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.

摘要翻译： 通路电路包括通过晶体管和体偏置控制电路，用于偏置通过晶体管的主体以减小体效应。 体偏置控制电路包括一个或多个控制晶体管，其布置成当预定电压施加到传输晶体管的漏极和栅极时，选择性地将传输晶体管的衬底（主体）连接到传输晶体管的漏极或栅极。 结果，通过晶体管在导通状态下表现出减小的体效应。 在一个实施例中，体偏置控制电路包括第一控制晶体管，其具有连接到传输晶体管的栅极的漏极和栅极，连接到传输晶体管的漏极的栅极和源极。 体偏置控制电路还包括第二控制晶体管，其具有连接到第一控制晶体管的源极的漏极，连接到传输晶体管的主体的源极和连接到通过晶体管的漏极的栅极。 传输晶体管，第一控制晶体管和第二控制晶体管的主体电互连。 通过这种布置，只有当传输晶体管的栅极和漏极都处于高电压电平时，传输晶体管的主体被传输晶体管的栅极偏置“高”。

公开(公告)号：US07859918B1

公开(公告)日：2010-12-28

申请号：US12577502

申请日：2009-10-12

申请人： Leon L. Nguyen ,  Martin L. Voogel

发明人： Leon L. Nguyen ,  Martin L. Voogel

IPC分类号： G11C7/00

CPC分类号： G11C5/147 ,  G05F3/242

摘要： A method and apparatus is provided for the implementation of a measurement and adjustment mechanism within a semiconductor die that facilitates adjustment of the magnitude of voltage generated by one or more voltage reference generation circuits on the die. In a first embodiment, the output voltage magnitude of a bandgap reference circuit may be measured and adjusted. In a second embodiment, the output voltage magnitude of a voltage regulator circuit may be measured and adjusted. Programmable circuit elements, such as programmable resistors, may first be programmed during a configuration event of the die to determine the optimal configuration settings of the one or more voltage reference generation circuits. The optimal configuration settings are then used to program the state of one or more eFuses to maintain the optimal configuration settings for the duration of the semiconductor die's lifetime.

摘要翻译： 提供了一种用于实现半导体管芯内的测量和调节机构的方法和装置，其有助于调节由管芯上的一个或多个电压基准产生电路产生的电压的大小。 在第一实施例中，可以测量和调整带隙基准电路的输出电压幅度。 在第二实施例中，可以测量和调整电压调节器电路的输出电压幅值。 可编程电路元件（例如可编程电阻器）可以首先在芯片的配置事件期间被编程以确定一个或多个电压基准产生电路的最佳配置设置。 然后，最佳配置设置用于编程一个或多个eFuse的状态，以在半导体芯片的使用寿命期间保持最佳配置设置。

公开(公告)号：US5986958A

公开(公告)日：1999-11-16

申请号：US16546

申请日：1998-01-30

申请人： Martin L. Voogel

发明人： Martin L. Voogel

IPC分类号： G11C11/404 ,  G11C11/405 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C11/405

摘要： Described are dynamic memory cells for use in FPGAs. Each memory cell includes a dynamic memory element that occupies less chip area than conventional static memory elements and that can be implemented using standard CMOS processes. In one embodiment, a conventional access transistor is connected to a pass transistor via a CMOS inverter. The CMOS inverter includes a pair of complementary MOS transistors sharing a common gate connection, and therefore exhibiting a combined gate capacitance. This gate capacitance at the input of the inverter supplements or replaces the capacitor normally required in conventional dynamic memory cells. Another embodiment uses the parasitic gate capacitance of a pass transistor for dynamic data storage. This embodiment requires that the voltage levels on the source and drain of the pass transistor be controlled during write and refresh operations to ensure that the gate capacitance of pass transistor stores an appropriate level of charge.

摘要翻译： 描述的是用于FPGA的动态存储单元。 每个存储单元包括动态存储器元件，其占用比常规静态存储器元件更少的芯片面积，并且可以使用标准CMOS工艺来实现。 在一个实施例中，传统的存取晶体管通过CMOS反相器连接到传输晶体管。 CMOS反相器包括共享公共栅极连接的一对互补MOS晶体管，因此呈现组合的栅极电容。 逆变器输入端的这个栅极电容补充或替代常规动态存储单元通常所需的电容器。 另一个实施例使用用于动态数据存储的传输晶体管的寄生栅极电容。 该实施例要求在写入和刷新操作期间控制传输晶体管的源极和漏极上的电压电平，以确保传输晶体管的栅极电容存储适当的电荷电平。

公开(公告)号：US5835402A

公开(公告)日：1998-11-10

申请号：US825236

申请日：1997-03-27

申请人： Kameswara K. Rao ,  Martin L. Voogel

发明人： Kameswara K. Rao ,  Martin L. Voogel

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C17/16 ,  G11C17/18 ,  G11C7/00

CPC分类号： G11C17/18 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C17/16

摘要： Non-volatile storage elements are provided on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are either one-time programmable devices which are programmed by rupturing their gate oxide, EEPROM floating gate transistor cells, or other EEPROM cells.

摘要翻译： 非易失性存储元件设置在集成电路上，其中非易失性存储元件是低电压CMOS器件，因此在制造意义上与集成电路上的其它类似晶体管兼容，从而不需要用于非集成电路的特殊类型的晶体管 非易失存储。 非易失性存储元件是通过破坏其栅极氧化物，EEPROM浮栅晶体管单元或其它EEPROM单元来编程的一次性可编程器件。

公开(公告)号：US07504877B1

公开(公告)日：2009-03-17

申请号：US11639546

申请日：2006-12-15

申请人： Martin L. Voogel ,  Ly Nguyen

发明人： Martin L. Voogel ,  Ly Nguyen

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/07

摘要： An integrated circuit including a voltage generator for generating a body bias voltage is described. The voltage generator includes a charge source and a voltage regulator coupled to the charge source. Transistors are coupled to the charge source to receive the body bias voltage from the voltage generator.

摘要翻译： 描述了包括用于产生体偏置电压的电压发生器的集成电路。 电压发生器包括电荷源和耦合到电荷源的电压调节器。 晶体管耦合到电荷源以接收来自电压发生器的体偏置电压。

公开(公告)号：US06621289B1

公开(公告)日：2003-09-16

申请号：US09896253

申请日：2001-06-28

申请人： Martin L. Voogel

发明人： Martin L. Voogel

IPC分类号： G01R3126

CPC分类号： H01L22/34

摘要： During the development of process parameters for fabricating an integrated circuit, a test circuit is provided on the wafer that provides rapid identification of process problems. Open circuits are identified by sequentially connecting one end of the conductive paths to the signal source and measuring the current at the other end. Short circuits are identified by sequentially connecting first conductive paths to the signal source and measuring the current generated in the second conductive paths. The location of breaks in the first conductive paths is identified by systematically bypassing sections of the first conductive paths, thereby facilitating failure analysis.

摘要翻译： 在制造集成电路的工艺参数的开发期间，在晶片上提供测试电路，其提供对工艺问题的快速识别。 通过将导电路径的一端顺序地连接到信号源并测量另一端的电流来识别开路。 通过将第一导电路径顺序地连接到信号源并测量在第二导电路径中产生的电流来识别短路。 通过系统地绕过第一导电路径的部分来识别第一导电路径中的断裂位置，从而有助于故障分析。

公开(公告)号：US06281696B1

公开(公告)日：2001-08-28

申请号：US09139629

申请日：1998-08-24

申请人： Martin L. Voogel

发明人： Martin L. Voogel

IPC分类号： G01R3126

CPC分类号： H01L22/34

摘要： During the development of process parameters for fabricating an integrated circuit, a test circuit is provided on the wafer that provides rapid identification of process problems (i.e., before failure analysis), detects defects down to a part-per-million (PPM) level, and identifies the precise location of any defects, thereby facilitating rapid failure analysis during the development and refinement of IC fabrication processes used to fabricate an integrated circuit (IC). In a first embodiment, the test circuit includes parallel conductive paths that are selectively connected to a signal source by pass transistors. Open circuits are identified by sequentially connecting one end of the conductive paths to the signal source and measuring the current at the other end. In a second embodiment, the test circuit includes perpendicular sets of overlapping conductors. Short conductive segments extend in parallel with a first set of conductors that are electrically connected to a second set of conductors. Short circuits are identified by sequentially connecting the first conductive paths to the signal source and measuring the current generated in the second conductive paths. In a third embodiment, the test circuit includes perpendicular sets of overlapping conductors. Pairs of parallel first conductors are selectively connected by bypass circuits. The location of breaks in the first conductors is identified by systematically bypassing sections of the first conductors, thereby facilitating failure analysis.

摘要翻译： 在开发用于制造集成电路的工艺参数的过程中，在晶片上提供测试电路，其提供对工艺问题的快速识别（即，在故障分析之前），将缺陷检测到百万分之一（PPM） 并识别任何缺陷的精确位置，从而有助于在用于制造集成电路（IC）的IC制造工艺的开发和细化过程中的快速故障分析。 在第一实施例中，测试电路包括通过传导晶体管选择性地连接到信号源的并行导电路径。 通过将导电路径的一端顺序地连接到信号源并测量另一端的电流来识别开路。 在第二实施例中，测试电路包括垂直的重叠导体组。 短导电段与电连接到第二组导体的第一组导体平行延伸。 通过将第一导电路径顺序地连接到信号源并测量在第二导电路径中产生的电流来识别短路。 在第三实施例中，测试电路包括垂直的重叠导体组。 成对的并联第一导体通过旁路电路选择性连接。 通过系统地绕过第一导体的部分来识别第一导体中的断裂位置，从而有助于故障分析。

公开(公告)号：US6055205A

公开(公告)日：2000-04-25

申请号：US262981

申请日：1999-03-05

申请人： Kameswara K. Rao ,  Martin L. Voogel

发明人： Kameswara K. Rao ,  Martin L. Voogel

IPC分类号： G11C16/08 ,  G11C8/00

CPC分类号： G11C16/08

摘要： A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process. The state of the low voltage storage transistor can be read through the p-channel transistor, or through a dedicated high voltage n-channel transistor. In one embodiment, the programming voltage is generated by a charge pump circuit fabricated in accordance with a standard sub 0.35 micron process. In another embodiment, the decoder circuits that access the non-volatile memory cell use high voltage p-channel transistors to transmit the high programming voltage. Another embodiment of the present invention includes a system-on-a-chip structure that implements the non-volatile memory of the present invention.

摘要翻译： 提供了一种非易失性存储单元，其包括具有共同连接到地的源极区和漏极区的低电压CMOS存储晶体管。 通过向其栅极施加高编程电压来编程低电压存储晶体管，从而破坏存储晶体管的栅极氧化物。 高编程电压通过高压p沟道晶体管施加到低电压存储晶体管。 高压p沟道晶体管具有比存储晶体管更厚的栅极氧化物，从而使得p沟道晶体管能够承受更高的电压。 高压p沟道晶体管也具有比相同尺寸的高电压n沟道晶体管更高的击穿电压。 低电压存储晶体管和高压p沟道晶体管都按照标准的次级0.35微米工艺制造。 低电压存储晶体管的状态可以通过p沟道晶体管或通过专用高压n沟道晶体管来读取。 在一个实施例中，编程电压由根据标准次级0.35微米工艺制造的电荷泵电路产生。 在另一个实施例中，访问非易失性存储单元的解码器电路使用高电压p沟道晶体管来传输高编程电压。 本发明的另一实施例包括实现本发明的非易失性存储器的片上系统结构。