公开(公告)号：US20090132768A1

公开(公告)日：2009-05-21

申请号：US12284331

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit capable of retrieving the portion of data from the system memory. The systems and methods further comprise a status memory for identifying whether or not a region of the cache memory contains data that has been accessed from the cache memory by an external device.

Abstract translation: 公开了包括用于存储存储在系统存储器中的数据的一部分的副本的高速缓存存储器和能够从系统存储器检索数据的部分的高速缓存加载电路的系统和方法。 系统和方法还包括状态存储器，用于识别高速缓冲存储器的区域是否包含通过外部设备从高速缓冲存储器访问过的数据。

公开(公告)号：US20130031347A1

公开(公告)日：2013-01-31

申请号：US13560294

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F9/00

CPC classification number: G06F9/4403 ,  G06F12/0638

Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.

Abstract translation: 一种第一装置，包括配置成从具有第一存储器空间的第二装置接收具有地址的事务的接口; 翻译器，被配置为将第一类型的接收到的事务的地址转换到第一布置的第二存储器空间，第二存储器空间不同于第一存储器空间; 以及引导逻辑，被配置为将所接收的事务的引导事务映射到所述第二存储器空间中的引导区域。

公开(公告)号：US20130031330A1

公开(公告)日：2013-01-31

申请号：US13560414

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/10

CPC classification number: G06F13/1657 ,  G06F13/14 ,  G06F13/385

Abstract: A first arrangement including a first interface configured to receive a memory transaction having an address from a second arrangement; a second interface; an address translator configured to determine based on said address if said transaction is for said first arrangement and if so to translate said address or if said transaction is for a third arrangement to forward said transaction without modification to said address to said second interface, said second interface being configured to transmit said transaction, without modification to said address, to said third arrangement.

Abstract translation: 一种第一装置，包括被配置为从第二装置接收具有地址的存储器事务的第一接口; 第二个接口; 地址转换器，被配置为基于所述地址确定所述交易是否用于所述第一布置，如果是，则转换所述地址，或者如果所述交易是用于第三种布置以将所述交易转发到所述第二接口的所述地址， 接口被配置为将所述交易传送到所述第三装置，而不改变所述地址。

公开(公告)号：US20110135046A1

公开(公告)日：2011-06-09

申请号：US12959005

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: H04L7/00

CPC classification number: H04L49/109 ,  G06F15/7825 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 在所述第一和第二模具中的至少一个上提供同步器。 同步器被配置为使得任何未发送的控制信号值跨接口传输。

公开(公告)号：US20110133826A1

公开(公告)日：2011-06-09

申请号：US12958744

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: H01L25/00

CPC classification number: G06F15/78 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 第一和第二裸片中的至少一个包括多个信号源，其中每个源具有与其相关联的至少一个服务质量参数，以及具有不同优先级的多个队列。 根据与相应信号源相关联的至少一个服务质量参数，来自相应信号源的信号被分配给多个队列中的一个。 接口被配置成使得来自所述队列的信号从所述第一和第二管芯中的一个传送到所述第一和第二管芯中的另一个。

公开(公告)号：US20090132749A1

公开(公告)日：2009-05-21

申请号：US12284329

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods are disclosed for pre-fetching data into a cache memory system. These systems and methods comprise retrieving a portion of data from a system memory and storing a copy of the retrieved portion of data in a cache memory. These systems and methods further comprise monitoring data that has been placed into pre-fetch memory.

Abstract translation: 公开了用于将数据预取入高速缓冲存储器系统的系统和方法。 这些系统和方法包括从系统存储器检索数据的一部分并且将检索到的数据部分的副本存储在高速缓冲存储器中。 这些系统和方法还包括监视已经被放置到预取存储器中的数据。

公开(公告)号：US09208096B2

公开(公告)日：2015-12-08

申请号：US12284332

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods for pre-fetching data are disclosed that use a cache memory for storing a copy of data stored in a system memory and mechanism to initiate a pre-fetch of data from the system memory into the cache memory. The system further comprises an event monitor for monitoring events that is connected to a path on which signals representing an event are transmitted between one or more event generating modules and a processor. In some embodiments, the event monitor initiates a pre-fetch of a portion of data in response to the event monitor detecting an event indicating the availability of the portion of data in the system memory.

Abstract translation: 公开了用于预取数据的系统和方法，其使用高速缓冲存储器来存储存储在系统存储器中的数据副本和机制，以发起从系统存储器预取数据到高速缓冲存储器中。 该系统还包括事件监视器，用于监视连接到一个路径上的事件，在该路径上，在一个或多个事件生成模块和处理器之间传送表示事件的信号。 在一些实施例中，响应于事件监视器检测指示系统存储器中的数据部分的可用性的事件，事件监视器启动对部分数据的预取。

公开(公告)号：US08504751B2

公开(公告)日：2013-08-06

申请号：US12960713

申请日：2010-12-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F13/24

CPC classification number: G06F13/24 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 该包装包括用于检测中断信息的中断处理和响应于中断信息检测提供分组。 分组包括要写入分组中的数据的地址。 该接口被配置为在信元之间传送数据包。 提供数据可写入的数据存储。 从几个数据包中接收的数据确定中断事件。

公开(公告)号：US08468381B2

公开(公告)日：2013-06-18

申请号：US12959005

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F1/04 ,  G06F12/00 ,  G06F15/00 ,  G06F11/00 ,  H04L7/00

CPC classification number: H04L49/109 ,  G06F15/7825 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 在所述第一和第二模具中的至少一个上提供同步器。 同步器被配置为使得任何未发送的控制信号值跨接口传输。

公开(公告)号：US20130031313A1

公开(公告)日：2013-01-31

申请号：US13560559

申请日：2012-07-27

Applicant: Stuart Ryan ,  Andrew Michael Jones

Inventor： Stuart Ryan ,  Andrew Michael Jones

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract translation: 一种第一高速缓存装置，包括被配置为从第二高速缓存装置接收存储器请求的输入; 用于存储数据的第一高速缓冲存储器; 输出，被配置为提供对所述第二高速缓存装置的所述存储器请求的响应; 和第一缓存控制器; 第一缓存控制器被配置为使得对于由输出输出的存储器请求的响应，高速缓存存储器不包括与存储器请求相关联的数据的分配。