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公开(公告)号：US10936785B2
公开(公告)日：2021-03-02
申请号：US16547065
申请日：2019-08-21
Inventor： Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang , Jia Han Lin
IPC: G06F30/398 , G06F119/18 , G03F7/20 , H01L27/092 , H01L27/02 , G06F30/392
Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.
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公开(公告)号：US10509888B1
公开(公告)日：2019-12-17
申请号：US16134419
申请日：2018-09-18
Inventor： Hiranmay Biswas , Kuo-Nan Yang , Chung-Hsing Wang
IPC: G06F17/50
Abstract: A method for forming an integrated device is provided. The method includes the following operations. A first circuit layout having a first power path and a second power path is provided. The first power path and the second power path are aligned in a first direction. A first pitch between the first power path and the second power path is analyzed. It is determined whether the first pitch is less than a threshold pitch. If the first pitch is less than the threshold pitch, the second power path is modified in a second direction. The second direction is perpendicular to the first direction.
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公开(公告)号：US09501602B2
公开(公告)日：2016-11-22
申请号：US14255325
申请日：2014-04-17
Inventor： Nitesh Katta , Jerry Chang-Jui Kao , Chin-Shen Lin , Yi-Chuin Tsai , Chou-Kun Lin , Kuo-Nan Yang , Chung-Hsing Wang
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5036 , G06F2217/78 , G06F2217/82 , G06F2217/84
Abstract: In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.
Abstract translation: 在一些实施例中，在一种方法中，执行设计布局的放置。 设计布局包括电力轨道段，几个上级电力线和几个电池。 上层电力线在电力轨道段上交叉并限制在上层电力线与电力轨道段相交的位置。 电池通过电源轨段供电。 对于每个电池，获得在电池的相应SW期间通过电力轨道段的相应电流。 确定具有重叠SW的一组或多组细胞。 获得使用每组单元的各自电流的一组或多组单元的电力轨道段的一个或多个EM用途。 当电力轨道段的一个或多个EM使用中的任何一个导致电力轨道段的EM敏感性时，调整设计布局。
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公开(公告)号：US20160329405A1
公开(公告)日：2016-11-10
申请号：US15212969
申请日：2016-07-18
Inventor： Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Kuo-Nan Yang , Ming-Hsiang Song , Ta-Pen Guo
IPC: H01L29/417 , H01L29/78 , H01L29/66 , H01L27/088
CPC classification number: H01L29/41775 , H01L21/823814 , H01L21/823821 , H01L27/0886 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/7851 , H01L2029/7858
Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance.
Abstract translation: 本发明涉及半导体器件的接触结构。 半导体器件的示例性结构包括在衬底上的绝缘区域; 绝缘区域上的栅极电极层，包括栅极中间线; 在与栅极电极层相邻的绝缘区域上的第一接触结构，包括第一中间线，其中第一中间线和栅极中间线具有第一距离; 以及在与包括第二中间线的第一接触结构相对的栅极电极层的一侧上的绝缘区域上的第二接触结构，其中第二中间线和栅极中间线具有大于第一距离的第二距离。
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公开(公告)号：US09367660B2
公开(公告)日：2016-06-14
申请号：US14218147
申请日：2014-03-18
Inventor： Nitesh Katta , Jerry Chang-Jui Kao , Chin-Shen Lin , Yi-Chuin Tsai , Chien-Ju Chao , Kuo-Nan Yang , Chung-Hsing Wang
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5031 , G06F17/5068 , G06F17/5072 , G06F17/5077
Abstract: In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.
Abstract translation: 在一些实施例中，在一种方法中，接收多个单元的单元布局。 对于每个单元，基于单元格布局中的单元的输出引脚的几何形状来确定影响要在设计布局中耦合到单元的输出引脚的互连的几何形状的相应约束。
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Patent Agency Ranking
公开(公告)号：US20160162619A1
公开(公告)日：2016-06-09
申请号：US15043858
申请日：2016-02-15
Inventor： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5081
Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
Abstract translation: 实施例小区移位方案包括将第一晶体管单元抵靠第二晶体管单元并将位置和布线边界移离设置在第一晶体管单元和第二晶体管单元之间的多晶硅。 在一个实施例中，小区移位方案包括移动位置和路由边界以防止布局与示意图（LVS）网表和后仿真网表之间的不匹配。
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公开(公告)号：US09287257B2
公开(公告)日：2016-03-15
申请号：US14470716
申请日：2014-08-27
Inventor： Chien-Ju Chao , Chou-Kun Lin , Yi-Chuin Tsai , Yen-Hung Lin , Po-Hsiang Huang , Kuo-Nan Yang , Chung-Hsing Wang
IPC: H01L27/06 , H01L27/02 , H01L23/528 , H01L23/50 , H01L21/768 , H01L21/324 , H01L21/8234
CPC classification number: H01L27/0207 , H01L21/324 , H01L21/768 , H01L21/8221 , H01L21/823475 , H01L21/823871 , H01L23/50 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L23/5329 , H01L27/0203 , H01L27/0688 , H01L27/092 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.
Abstract translation: 在本公开中描述了在多个有源器件层上形成功率门控单元和虚拟功率电路的机构的实施例。 电源门控单元和虚拟电源电路形成在单独的有源器件层上，以允许与电源连接的互连结构形成在与用于连接电源门控单元和虚拟电源电路的互连结构的单独级别上。 这种分离防止这两种类型的互连结构竞争相同的空间。 两种类型的互连结构的路由变得更加容易。 结果，互连结构的金属长度减小并且金属宽度增加。 减少金属长度和增加的金属宽度降低电阻，提高电阻 - 电容（RC）延迟和电气性能，并提高互连可靠性，如减少电迁移。
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公开(公告)号：US08847284B2
公开(公告)日：2014-09-30
申请号：US13829484
申请日：2013-03-14
Inventor： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
CPC classification number: H01L27/0207 , H01L27/11807
Abstract: A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region.
Abstract translation: 芯片包括多行标准单元。 多行标准单元中的每个标准单元包括晶体管和源极边缘，其中晶体管的源极区域与源极边缘相邻。 所有标准单元中的每一个中的任何晶体管的漏极区域都不与源极区域相邻。
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公开(公告)号：US20140239412A1
公开(公告)日：2014-08-28
申请号：US13874055
申请日：2013-04-30
Inventor： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC: H01L27/07
CPC classification number: H01L29/66545 , H01L21/823412 , H01L27/0207 , H01L27/0705 , H01L27/11807
Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.
Abstract translation: 集成电路包括第一和第二标准单元。 第一标准单元包括第一栅极电极和第一栅极电极下面的第一沟道区域。 第一通道区域具有第一通道掺杂浓度。 第二标准单元包括第二栅极电极和第二栅极电极下面的第二沟道区域。 第二沟道区具有第二沟道掺杂浓度。 虚拟栅极分别包括第一和第二标准单元中的前半部分和第二半部分。 第一半和第二半分别在第一标准单元和第二标准单元的边缘处并且彼此抵接。 虚拟通道由虚拟门重叠。 虚拟通道具有基本上等于第一通道掺杂浓度和第二通道掺杂浓度之和的第三通道掺杂浓度。
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公开(公告)号：US20140183632A1
公开(公告)日：2014-07-03
申请号：US13730052
申请日：2012-12-28
Inventor： Hsiang-Jen Tseng , Ting-Wei Chang , Wei-Yu Chen , Kuo-Nan Yang , Ming-Hsiang Song , Ta-Pen Guo
CPC classification number: H01L29/41775 , H01L27/0886 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance.
Abstract translation: 本发明涉及半导体器件的接触结构。 半导体器件的示例性结构包括在衬底上的绝缘区域; 绝缘区域上的栅极电极层，包括栅极中间线; 在与栅极电极层相邻的绝缘区域上的第一接触结构，包括第一中间线，其中第一中间线和栅极中间线具有第一距离; 以及在与包括第二中间线的第一接触结构相对的栅极电极层的一侧上的绝缘区域上的第二接触结构，其中第二中间线和栅极中间线具有大于第一距离的第二距离。
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