公开(公告)号：US10325900B2

公开(公告)日：2019-06-18

申请号：US16051241

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L29/423 ,  H01L27/118

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US20190067185A1

公开(公告)日：2019-02-28

申请号：US16174953

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue

IPC: H01L23/522 ,  H01L27/02

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US09478609B2

公开(公告)日：2016-10-25

申请号：US14328408

申请日：2014-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Wei Chiang ,  Li-Chun Tien ,  Ming-Jin Huang ,  Pin-Dai Sue

IPC: G06F17/50 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L29/0657 ,  G06F17/5072 ,  H01L27/0207

Abstract: An integrated circuit comprises a first cell having first cell height and a first line routed at a first line height and having a first line width. The integrated circuit also comprises a second cell having a second cell height different from the first cell height and a second line routed at a second line height and a second line width different from the first line width. The integrated circuit further comprises a third cell. The third cell has a third line having a first end and a second end. The first end has a first end width. The second end has a second end width. The first end width is equal to the first line width. The second end width is equal to the second line width. The first end is coupled with the first line. The second end is coupled with the second line.

Abstract translation: 集成电路包括具有第一单元高度的第一单元和以第一行高度布线且具有第一行宽的第一行。 集成电路还包括具有不同于第一单元高度的第二单元高度的第二单元和以第二行高度路由的第二行和与第一行宽不同的第二行宽。 集成电路还包括第三单元。 第三单元具有具有第一端和第二端的第三线。 第一端具有第一端宽度。 第二端具有第二端宽。 第一个末端宽度等于第一个线宽。 第二端宽等于第二线宽。 第一端与第一行相结合。 第二端与第二线连接。

公开(公告)号：US09478540B2

公开(公告)日：2016-10-25

申请号：US14220930

申请日：2014-03-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsong-Hua Ou ,  Shu-Min Chen ,  Pin-Dai Sue ,  Li-Chun Tien ,  Ru-Gun Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/118 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0924 ,  H01L27/11803

Abstract: A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

Abstract translation: 设计标准单元的方法包括确定标准单元中的半导体鳍片的最小鳍间距，其中半导体鳍片是FinFET的部分; 以及确定所述标准单元上的底部金属层中的金属线的最小金属间距，其中所述最小金属间距大于所述最小鳍间距。 将标准单元放置在集成电路中并在半导体晶片上实现。

公开(公告)号：US12277379B2

公开(公告)日：2025-04-15

申请号：US18448149

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Hui-Zhong Zhuang ,  Meng-Kai Hsu ,  Pin-Dai Sue ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu ,  Jung-Chou Tsai

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F119/18

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

公开(公告)号：US12237322B2

公开(公告)日：2025-02-25

申请号：US18413078

申请日：2024-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shun-Li Chen ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Jung-Chan Yang

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.

公开(公告)号：US20240387547A1

公开(公告)日：2024-11-21

申请号：US18785700

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Lun Chien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue

IPC: H01L27/092 ,  H01L21/765 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

公开(公告)号：US11995390B2

公开(公告)日：2024-05-28

申请号：US18064000

申请日：2022-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yu Lu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jerry Chang Jui Kao ,  Pin-Dai Sue ,  Jiun-Jia Huang ,  Yu-Ti Su ,  Wei-Hsiang Ma

IPC: G06F30/394 ,  G03F1/36 ,  G03F1/70 ,  G06F30/398

CPC classification number: G06F30/394 ,  G03F1/36 ,  G03F1/70 ,  G06F30/398

Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.

公开(公告)号：US20240105726A1

公开(公告)日：2024-03-28

申请号：US18517938

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Lun Chien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue

IPC: H01L27/092 ,  H01L21/765 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/765 ,  H01L21/823412 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922

Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

公开(公告)号：US11935888B2

公开(公告)日：2024-03-19

申请号：US16837497

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pin-Dai Sue ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Ya-Chi Chou ,  Chi-Yu Lu

IPC: H01L27/118 ,  G06F30/367 ,  G06F30/392 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/088 ,  G06F119/06

CPC classification number: H01L27/0886 ,  G06F30/367 ,  G06F30/392 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  G06F2119/06

Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.