公开(公告)号：US20180254255A1

公开(公告)日：2018-09-06

申请号：US15449361

申请日：2017-03-03

Applicant: TDK CORPORATION

Inventor： Makoto ORIKASA ,  Hideyuki SEIKE ,  Yuhei HORIKAWA ,  Hisayuki ABE

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05655 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1181 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/16148 ,  H01L2224/81014 ,  H01L2224/81035 ,  H01L2224/81047 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/81143 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/00012

Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.

公开(公告)号：US20140291021A1

公开(公告)日：2014-10-02

申请号：US14219766

申请日：2014-03-19

Applicant: TDK CORPORATION

Inventor： Kenichi YOSHIDA ,  Yuhei HORIKAWA ,  Hisayuki ABE

IPC: H01R4/02

CPC classification number: H01R4/02 ,  B23K35/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/16238 ,  H01L2224/16502 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81825 ,  H01L2924/01322 ,  H05K3/3463 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A junction structure for electronic device having an excellent bonding strength is provided. A junction structure for electronic device in accordance with one aspect of the present invention includes a first metal layer containing nickel and a second metal layer containing gold, tin, and nickel, while the second metal layer includes an AuSn eutectic phase.

Abstract translation: 提供了具有优异的接合强度的电子器件的接合结构。 根据本发明的一个方面的用于电子器件的接合结构包括含有镍的第一金属层和含有金，锡和镍的第二金属层，而第二金属层包括AuSn共晶相。

公开(公告)号：US20140054769A1

公开(公告)日：2014-02-27

申请号：US13960291

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi YOSHIDA ,  Makoto ORIKASA ,  Hideyuki SEIKE ,  Yuhei HORIKAWA ,  Hisayuki ABE

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.

Abstract translation: 优选的端子结构包括基材; 形成在基材上的电极; 绝缘覆盖层，形成在所述基底材料上和所述电极上，并且具有暴露所述电极的至少一部分的开口; 含有Ni的下凸块金属层，填充电极上的开口; 以及包含Sn和Ti的圆顶状凸起，覆盖下凸块状金属层，其中至少部分下凸块金属层具有夹在外部电极和绝缘覆盖层之间的部分。

公开(公告)号：US20130192873A1

公开(公告)日：2013-08-01

申请号：US13678107

申请日：2012-11-15

Applicant: TDK CORPORATION

Inventor： Makoto ORIKASA ,  Hideyuki SEIKE ,  Noboru ITO ,  Kenichi YOSHIDA ,  Yuhei HORIKAWA

IPC: H01B1/00

CPC classification number: H01B1/00 ,  H01B1/026

Abstract: This structure body includes a conductor comprising Cu as a main component, an intermediate layer formed on the conductor, and a protective layer formed on the intermediate layer, the intermediate layer includes at least Cu, Sn, Ni, and P, and the protective layer includes at least Ni and P.

Abstract translation: 该结构体包括以Cu为主要成分的导体，形成在导体上的中间层和形成在中间层上的保护层，中间层至少包括Cu，Sn，Ni和P，保护层 至少包括Ni和P.