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公开(公告)号：US20130130059A1
公开(公告)日：2013-05-23
申请号：US13677509
申请日：2012-11-15
Applicant: TDK CORPORATION
Inventor： Kenichi YOSHIDA , Yuhei HORIKAWA , Makoto ORIKASA , Hideyuki SEIKE
CPC classification number: H01B1/026 , C22C5/04 , C23C18/1651 , C23C18/34 , C23C18/44 , C23C18/54 , H01B1/02 , Y10T428/12701 , Y10T428/12722 , Y10T428/12778 , Y10T428/12861 , Y10T428/12889 , Y10T428/12903
Abstract: A coating is provided to a conductor, and has a layered structure of a palladium layer. The palladium layer has a crystal plane whose orientation rate is 65% or more.
Abstract translation: 向导体提供涂层，并且具有钯层的层状结构。 钯层具有取向率为65％以上的晶面。
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公开(公告)号：US20140054768A1
公开(公告)日：2014-02-27
申请号：US13960228
申请日：2013-08-06
Applicant: TDK CORPORATION
Inventor： Kenichi YOSHIDA , Makoto ORIKASA , Hideyuki SEIKE , Yuhei HORIKAWA , Hisayuki ABE
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05655 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13006 , H01L2224/13023 , H01L2224/13111 , H01L2924/00014 , H01L2924/00012 , H01L2924/207 , H01L2224/05552
Abstract: The present invention relates to a terminal structure comprising: a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, a height Hbm at which the bump has a maximum diameter (Lbm) is lower than a maximum height Hu of the under-bump metal layer.
Abstract translation: 本发明涉及一种端子结构，包括：基材10; 形成在基材上的外部电极20; 绝缘涂层30，形成在基材和电极上，并具有露出电极的至少一部分的开口; 填充绝缘涂层的开口和覆盖部分的凸块下金属层70; 以及覆盖凸块下金属层的圆顶状凸起85，其中在沿着层叠方向的截面中，所述凸块具有最大直径（Lbm）的高度Hbm低于所述凸块下凸块的最大高度Hu， 凸块金属层。
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3.发明申请TERMINAL STRUCTURE, AND SEMICONDUCTOR ELEMENT AND MODULE SUBSTRATE COMPRISING THE SAME 有权端子结构和包含其的半导体元件和模块基板公开(公告)号：US20140054770A1
公开(公告)日：2014-02-27
申请号：US13960330
申请日：2013-08-06
Applicant: TDK CORPORATION
Inventor： Kenichi YOSHIDA , Makoto ORIKASA , Hideyuki SEIKE , Yuhei HORIKAWA , Hisayuki ABE
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/03462 , H01L2224/0347 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05571 , H01L2224/05655 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/13006 , H01L2224/13017 , H01L2224/13022 , H01L2224/13076 , H01L2224/13111 , H01L2924/00014 , H01L2224/05572 , H01L2924/00015 , H01L2924/00012 , H01L2224/05552
Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, formed in a region in the opening on the electrode so that an upper surface of the metal layer is at a position lower than an upper surface of the insulating covering layer in a peripheral edge portion of the opening; and a dome-shaped bump containing Sn and Ti, formed in a region in the opening on the under bump metal layer, wherein an end portion of a boundary between the under bump metal layer and the bump is in contact with an inner wall of the opening portion in the insulating covering layer.
Abstract translation: 优选的端子结构包括基材; 形成在基材上的电极; 绝缘覆盖层，形成在所述基底材料上和所述电极上，并且具有暴露所述电极的至少一部分的开口; 在所述电极的开口部的区域形成含有Ni的下凸块金属层，使得所述金属层的上表面位于比所述开口的周缘部的所述绝缘覆盖层的上表面低的位置; 以及形成在下凸块金属层的开口部的区域中的包含Sn和Ti的圆顶状的凸部，其中，下凸块状金属层与凸块之间的边界的端部与内凸块 绝缘覆盖层的开口部。
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公开(公告)号：US20140054767A1
公开(公告)日：2014-02-27
申请号：US13960173
申请日：2013-08-06
Applicant: TDK CORPORATION
Inventor： Kenichi YOSHIDA , Makoto ORIKASA , Hideyuki SEIKE , Yuhei HORIKAWA , Hisayuki ABE
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05655 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13006 , H01L2224/13023 , H01L2224/13111 , H01L2924/00014 , H01L2224/05552
Abstract: The present invention relates to a terminal structure comprising; a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, the under-bump metal layer has a convex shape toward the bump, and the thickness Tu0 of the under-bump metal layer at a center of the opening is equal to or greater than the thickness Tu1 of the under-bump metal layer at an end portion of the opening.
Abstract translation: 本发明涉及一种终端结构，包括： 基材10; 形成在基材上的外部电极20; 绝缘涂层30，形成在基材和电极上，并具有露出电极的至少一部分的开口; 填充绝缘涂层的开口和覆盖部分的凸块下金属层70; 以及覆盖凸块下金属层的圆顶状凸起85，其中沿着层叠方向的截面中，凸块下金属层朝向凸块呈凸形，凸块下金属层的厚度Tu0 在开口的中心处等于或大于开口端部处的凸块下金属层的厚度Tu1。
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Patent Agency Ranking
公开(公告)号：US20130126208A1
公开(公告)日：2013-05-23
申请号：US13678033
申请日：2012-11-15
Applicant: TDK CORPORATION
Inventor： Kenichi YOSHIDA , Yuhei HORIKAWA , Makoto ORIKASA , Hideyuki SEIKE
IPC: H01B1/02
CPC classification number: H01B1/02 , H01L2224/85444
Abstract: A coating is provided to a conductor, and has a layered structure of a palladium layer. The palladium layer is amorphous and contains phosphorus in a concentration ranging from 7.3% by mass to 11.0% by mass.
Abstract translation: 向导体提供涂层，并且具有钯层的层状结构。 钯层为无定形，含有浓度为7.3质量％〜11.0质量％的磷。
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公开(公告)号：US20190013293A1
公开(公告)日：2019-01-10
申请号：US16037537
申请日：2018-07-17
Applicant: TDK CORPORATION
Inventor： Makoto ORIKASA , Hideyuki SEIKE , Yuhei HORIKAWA , Hisayuki ABE
IPC: H01L23/00 , H01L25/065 , H01L25/00
CPC classification number: H01L24/81 , H01L24/11 , H01L24/13 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05655 , H01L2224/11005 , H01L2224/11334 , H01L2224/1146 , H01L2224/1181 , H01L2224/1184 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16148 , H01L2224/81002 , H01L2224/81014 , H01L2224/81022 , H01L2224/81035 , H01L2224/81047 , H01L2224/81048 , H01L2224/81065 , H01L2224/81143 , H01L2224/81815 , H01L2224/95146 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01015 , H01L2924/00012 , H01L2924/01047 , H01L2924/014 , H01L2924/01029 , H01L2924/01083
Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.
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公开(公告)号：US20180254255A1
公开(公告)日：2018-09-06
申请号：US15449361
申请日：2017-03-03
Applicant: TDK CORPORATION
Inventor： Makoto ORIKASA , Hideyuki SEIKE , Yuhei HORIKAWA , Hisayuki ABE
IPC: H01L23/00 , H01L25/00 , H01L25/065
CPC classification number: H01L24/81 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2224/05655 , H01L2224/11005 , H01L2224/11334 , H01L2224/1146 , H01L2224/1181 , H01L2224/1184 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/16148 , H01L2224/81014 , H01L2224/81035 , H01L2224/81047 , H01L2224/81048 , H01L2224/81065 , H01L2224/81143 , H01L2224/81815 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01015 , H01L2924/00012
Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.
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8.发明申请TERMINAL STRUCTURE, AND SEMICONDUCTOR ELEMENT AND MODULE SUBSTRATE COMPRISING THE SAME 有权端子结构和包含其的半导体元件和模块基板公开(公告)号：US20140054769A1
公开(公告)日：2014-02-27
申请号：US13960291
申请日：2013-08-06
Applicant: TDK CORPORATION
Inventor： Kenichi YOSHIDA , Makoto ORIKASA , Hideyuki SEIKE , Yuhei HORIKAWA , Hisayuki ABE
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/03462 , H01L2224/0347 , H01L2224/0401 , H01L2224/05022 , H01L2224/05571 , H01L2224/05655 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/13006 , H01L2224/13017 , H01L2224/13022 , H01L2224/13111 , H01L2924/00014 , H01L2924/00015 , H01L2924/00012 , H01L2224/05552
Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.
Abstract translation: 优选的端子结构包括基材; 形成在基材上的电极; 绝缘覆盖层，形成在所述基底材料上和所述电极上，并且具有暴露所述电极的至少一部分的开口; 含有Ni的下凸块金属层，填充电极上的开口; 以及包含Sn和Ti的圆顶状凸起，覆盖下凸块状金属层，其中至少部分下凸块金属层具有夹在外部电极和绝缘覆盖层之间的部分。
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9.发明申请STRUCTURE BODY AND ELECTRONIC COMPONENT AND PRINTED WIRING BOARD INCLUDING THE SAME 审中-公开结构体和电子元件和印刷线路板包括它们公开(公告)号：US20130192873A1
公开(公告)日：2013-08-01
申请号：US13678107
申请日：2012-11-15
Applicant: TDK CORPORATION
Inventor： Makoto ORIKASA , Hideyuki SEIKE , Noboru ITO , Kenichi YOSHIDA , Yuhei HORIKAWA
IPC: H01B1/00
Abstract: This structure body includes a conductor comprising Cu as a main component, an intermediate layer formed on the conductor, and a protective layer formed on the intermediate layer, the intermediate layer includes at least Cu, Sn, Ni, and P, and the protective layer includes at least Ni and P.
Abstract translation: 该结构体包括以Cu为主要成分的导体，形成在导体上的中间层和形成在中间层上的保护层，中间层至少包括Cu，Sn，Ni和P，保护层 至少包括Ni和P.
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