公开(公告)号：US20230065509A1

公开(公告)日：2023-03-02

申请号：US17462743

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Hiroyuki Tomomatsu

IPC: H01L27/06 ,  H01L29/778 ,  H01L29/66 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

公开(公告)号：US10192799B2

公开(公告)日：2019-01-29

申请号：US16010654

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: G01R31/28 ,  G01R31/12 ,  H01L27/08 ,  H01L29/41 ,  H01L29/20 ,  H01L29/40 ,  H01L29/06 ,  H01L21/66 ,  H01L27/088 ,  H01L29/417 ,  H01L23/544

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US10134596B1

公开(公告)日：2018-11-20

申请号：US15820168

申请日：2017-11-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Yoshikazu Kondo ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/205 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L21/02

Abstract: In some embodiments, an apparatus includes a first layer with a first surface and a second surface opposite to the first surface. The apparatus also includes a second layer having a third surface interfacing the second surface and a fourth surface opposite the third surface. The apparatus further includes a third layer having a fifth surface interfacing the fourth surface and a sixth surface opposite the fifth surface. The apparatus also includes a fourth layer having a seventh surface interfacing the sixth surface to form a heterojunction, which generates a two-dimensional electron gas channel formed in the fourth layer. Further, the apparatus includes a recess that extends from the first surface to the fifth surface.

公开(公告)号：US20180308773A1

公开(公告)日：2018-10-25

申请号：US16010654

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L21/66 ,  G01R31/28 ,  H01L27/088 ,  H01L29/06 ,  H01L23/544 ,  H01L29/20 ,  H01L29/417 ,  G01R31/12 ,  H01L29/40

CPC classification number: H01L22/34 ,  G01R31/12 ,  G01R31/2621 ,  G01R31/2642 ,  H01L23/544 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/41725

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US20250006593A1

公开(公告)日：2025-01-02

申请号：US18345939

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Hiroshi Yamasaki ,  Hisayuki Shimada ,  Kenichi Yoshikawa

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L29/20

Abstract: A microelectronic device includes a semiconductor substrate with a III-N semiconductor layer over the semiconductor substrate. A substrate via opening extending through the III-N semiconductor layer and a substrate contact pad in the substrate via opening, contacting the semiconductor substrate provide a substrate contact. The microelectronic device also includes an inter-level dielectric layer with a planar surface over the substrate contact. The microelectronic device further includes an interconnect metal level over the inter-level dielectric layer. The substrate via opening is formed through the III-N semiconductor layer to expose the semiconductor substrate. The substrate contact pad is formed over the III-N semiconductor layer, extending into the substrate via opening and making contact with the semiconductor substrate, to form the substrate contact. The ILD layer is formed over the III-N semiconductor layer and the substrate contact pad, so that the ILD layer has a planar surface over the substrate via opening.

公开(公告)号：US12166119B2

公开(公告)日：2024-12-10

申请号：US18357431

申请日：2023-07-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20240322006A1

公开(公告)日：2024-09-26

申请号：US18189870

申请日：2023-03-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/7786

Abstract: A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of a GaN semiconductor material. The GaN FET includes a contact etch stop and a stretch contact electrically connecting a source region with the contact etch stop. The contact etch stop may stretch over a p-type GaN gate structure towards a drain region to form a field plate connected to the source region. The contact etch stop provides a method to connect the field plate to the source region which allows efficient area scaling of space between the source region and the p-GaN gate structure. Disclosed examples provide an associated process flow for forming such GaN FETs.

公开(公告)号：US20240055488A1

公开(公告)日：2024-02-15

申请号：US17885879

申请日：2022-08-11

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Chang Soo Suh

IPC: H01L29/20 ,  H01L21/285 ,  H01L29/51

CPC classification number: H01L29/2003 ,  H01L21/28581 ,  H01L29/518

Abstract: A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of p-type GaN semiconductor material. The GaN FET includes a gate electrode extension of p-type GaN semiconductor material in electrical contact with the gate electrode. The gate electrode extension of p-type GaN semiconductor material in electrical contact with the gate electrode may improve the GaN FET characteristics such as off state leakage, subthreshold voltage and post stress Vt shift.

公开(公告)号：US20230411461A1

公开(公告)日：2023-12-21

申请号：US17806959

申请日：2022-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Qhalid Fareed

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L21/0254

Abstract: A semiconductor device is described herein. The semiconductor device comprises a silicon substrate layer. The semiconductor device comprises a first semiconductor layer comprising a gallium nitride layer, the first semiconductor layer disposed over the silicon substrate layer. The semiconductor device comprises a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer comprising an aluminum gallium nitride layer. The semiconductor device comprises a first drain contact extending through the second semiconductor layer and extending into the first semiconductor layer.

公开(公告)号：US11742390B2

公开(公告)日：2023-08-29

申请号：US17085558

申请日：2020-10-30

Applicant: Texas Instruments Incorporated

Inventor： Qhalid R S Fareed ,  Dong Seup Lee ,  Nicholas S. Dellas

IPC: H01L29/15 ,  H01L21/02

CPC classification number: H01L29/151 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02532

Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.