公开(公告)号：US20190331765A1

公开(公告)日：2019-10-31

申请号：US16442152

申请日：2019-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Rao ,  Karthik Ramasubramanian ,  Indu Prathapan ,  Raghu Ganesan ,  Pankaj Gupta

IPC: G01S7/02 ,  G01S13/58 ,  G01S7/35 ,  G01S13/42 ,  G01S13/34 ,  H04B15/02 ,  H04L27/10

Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

公开(公告)号：US20180227157A1

公开(公告)日：2018-08-09

申请号：US15942614

申请日：2018-04-02

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi ,  Pankaj Gupta ,  Indu Prathapan

IPC: H04L27/26

CPC classification number: H04L27/2624

Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

公开(公告)号：US09374678B2

公开(公告)日：2016-06-21

申请号：US14194449

申请日：2014-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Sthanunathan Ramakrishnan ,  Jaiganesh Balakrishnan ,  Sachin Bhardwaj

IPC: H04W4/04

CPC classification number: H04W4/043

Abstract: Several systems and methods for location estimation in a multi-floor environment are disclosed. In an embodiment, the method includes performing wireless scanning so as to receive wireless signals from one or more access points from among a plurality of access points positioned at plurality of locations, respectively at one or more floors from among a plurality of floors within the multi-floor environment. A first set of RSSI measurements is computed corresponding to the wireless signals. Absolute floor location information is determined based on the first set of RSSI measurements and a pre-defined objective function. The pre-defined objective function is configured to maximize a probability of a user being located at a floor so as to receive the wireless signals. A user floor location is determined based on the absolute floor location information. The user location is estimated at least in part based on the user floor location.

Abstract translation: 公开了用于多层环境中的位置估计的几种系统和方法。 在一个实施例中，该方法包括执行无线扫描，以便从位于多个接入点内的多个接入点中的多个接入点接收无线信号，所述多个接入点分别位于多个接入点内的多个接入点 - 地板环境。 对应于无线信号计算第一组RSSI测量。 基于第一组RSSI测量和预定义的目标函数来确定绝对楼层位置信息。 预定义的目标函数被配置为最大化用户位于楼层的概率以便接收无线信号。 基于绝对楼层位置信息确定用户楼层位置。 至少部分地基于用户楼层位置来估计用户位置。

公开(公告)号：US20160127161A1

公开(公告)日：2016-05-05

申请号：US14528660

申请日：2014-10-30

Applicant: Texas Instruments Incorporated

Inventor： Sriram Murali ,  Indu Prathapan ,  Pankaj Gupta ,  Zahir Ibrahim Parkar ,  Sundarrajan Rangachari

IPC: H04L27/156 ,  H04L27/38 ,  H04L27/34 ,  H04L27/14

CPC classification number: H04L27/1566 ,  H04L27/3455 ,  H04W52/0229 ,  Y02D70/00

Abstract: A weather band receiver, which may be part of an FM receiver, is disclosed. FSK-encoded data units in an alert packet transmission are detected using a quadrature matched filter circuit. At least one FSK-encoded data unit is captured from the alert packet transmission. Soft quantized bits are extracted from the FSK-encoded data units. The soft quantized bits are saved to memory and used to recover an alert message. Soft quantized bits from two or more FSK-encoded data units may be combined before recovering the alert message.

Abstract translation: 公开了可以是FM接收机的一部分的气象带接收机。 使用正交匹配滤波器电路检测警报分组传输中的FSK编码数据单元。 从警报包传输中捕获至少一个FSK编码的数据单元。 从FSK编码数据单元提取软量化比特。 软量化位保存到存储器中，用于恢复警报消息。 可以在恢复警报消息之前组合来自两个或更多个FSK编码数据单元的软量化比特。

公开(公告)号：US12141544B2

公开(公告)日：2024-11-12

申请号：US18335452

申请日：2023-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Puneet Sabbarwal ,  Pankaj Gupta

IPC: G06F7/24 ,  G06F5/06

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

公开(公告)号：US12130378B2

公开(公告)日：2024-10-29

申请号：US17572714

申请日：2022-01-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Karthik Ramasubramanian

IPC: G01S7/35 ,  G06F17/14 ,  G06F17/16 ,  H04L27/26

CPC classification number: G01S7/352 ,  G06F17/142 ,  H04L27/265 ,  G01S7/356 ,  G06F17/141 ,  G06F17/16 ,  H04L27/263

Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

公开(公告)号：US12057854B2

公开(公告)日：2024-08-06

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

公开(公告)号：US20240184846A1

公开(公告)日：2024-06-06

申请号：US18129589

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Mathews John ,  Pankaj Gupta ,  Jawaharlal Tangudu ,  Pankaj Gaur ,  Shikhar Chouhan ,  Manchi Sankalkar Ajay

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: An example apparatus includes: programmable circuitry to receive an input signal, a digital pre-distorter (DPD) output signal, and a power amplifier (PA) feedback signal; populate a partial matrix with a threshold number of rows of equation terms; compute a respective observation terms for each row in the threshold number of rows; reduce the partial matrix into a Hermitian matrix and reduce the observation terms into a vector; accumulate the Hermitian matrix and the vector onto the memory; regularize, after a determination that a threshold number of Hermitian matrices have been accumulated, the memory to form an output matrix; and pre-distort the input signal using the output matrix.

公开(公告)号：US11428777B2

公开(公告)日：2022-08-30

申请号：US16208276

申请日：2018-12-03

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Sriram Murali ,  Karthik Ramasubramanian

IPC: G01S7/35 ,  G01S13/34 ,  H03D1/22 ,  G01S7/40 ,  H03D7/16 ,  H03D3/00 ,  G01S13/931

Abstract: A FMCW radar receiver includes a LO providing a chirped LO signal, an in-phase (I) channel for outputting I-data and a quadrature (Q) channel for outputting Q-data. A dynamic correction parameter generator generates IQ phase correction values (P[n]s) and IQ gain correction values (G[n]s) based on a frequency slope rate of the chirped LO signal for generating during intervals of chirps including a first sequence of P[n]s and G[n]s during a first chirp and a second sequence of P[n]s and G[n]s during a second chirp. An IQ mismatch (IQMM) correction circuit has a first IQMM input coupled to receive the I-data and a second IQMM input receiving the Q-data, and the P[n]s and G[n]s. During the first chirp the IQMM correction circuit provides first Q′-data and first I′-data and during the second chirp the IQMM correction circuit provides at least second Q′-data and second I′-data.

公开(公告)号：US11251803B2

公开(公告)日：2022-02-15

申请号：US17063037

申请日：2020-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Jawaharlal Tangudu ,  Ajai Paulose

IPC: H03M1/06 ,  H03M1/10 ,  H03M3/00 ,  H03M1/12

Abstract: A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.