公开(公告)号：US10484001B1

公开(公告)日：2019-11-19

申请号：US16221464

申请日：2018-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi Soundararajan ,  Visvesvaraya Pentakota ,  Anand Jerry George

IPC: H03M1/46 ,  H03M1/68 ,  H03M1/12 ,  H03M1/06

Abstract: A system for digitizing a sampled input value includes a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes, and a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles. Dither is dynamically added to the digital-to-analog converter in the intermediate cycle. The dither is corrected for in the subsequent cycle.

公开(公告)号：US10038453B1

公开(公告)日：2018-07-31

申请号：US15792924

申请日：2017-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Jerry George ,  Rishi Soundararajan ,  Visvesvaraya Pentakota

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/80 ,  H03M1/68 ,  H03M1/46

CPC classification number: H03M1/1061 ,  H03M1/0604 ,  H03M1/468 ,  H03M1/68 ,  H03M1/802 ,  H03M1/804

Abstract: An analog-to-digital converter includes a comparator, a capacitive digital-to-analog converter (DAC), and calibration circuitry. The capacitive DAC is coupled to the comparator, and includes a plurality of capacitors. The calibration circuitry is configured to adjust a value of each of the capacitors, and includes binary search circuitry and error correction circuitry. The binary search circuitry applies a binary search over a first number of bits of a multi-bit adjustment value used to adjust the value of one of the capacitors, and averages a first number of comparator output samples to determine each of the first number of bits. The error correction circuitry applies an error correction to the multi-bit adjustment value generated by the binary search, and averages a second number of comparator output samples for the error correction. The second number of comparator output samples is greater than the first number of comparator output samples.

公开(公告)号：US20180191362A1

公开(公告)日：2018-07-05

申请号：US15909378

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/16 ,  H03M1/36

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US09941893B2

公开(公告)日：2018-04-10

申请号：US15485552

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US20180069566A1

公开(公告)日：2018-03-08

申请号：US15466691

申请日：2017-03-22

Applicant: Texas Instruments Incorporated

Inventor： Rishi Soundararajan

IPC: H03M1/46 ,  H03K5/24 ,  H03M1/06

CPC classification number: H03M1/46 ,  H03K5/2481 ,  H03M1/0607 ,  H03M1/36 ,  H03M1/44 ,  H03M1/48

Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.