公开(公告)号：US09013226B2

公开(公告)日：2015-04-21

申请号：US13627396

申请日：2012-09-26

Applicant: Texas Instruments Incorporated

Inventor： Shagun Dusad ,  Visvesvaraya Pentakota

IPC: H03K17/16

CPC classification number: H03K17/16 ,  H03F1/32 ,  H03F3/45179 ,  H03F2203/45394 ,  H03F2203/45684 ,  H03F2203/45702 ,  H03K17/165

Abstract: Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate.

Abstract translation: 提供了构造成改善以线性区域工作的金属氧化物半导体（MOS）晶体管的二阶谐波失真的电路的各种实施例。 在一个实施例中，电路包括平均电路，其被配置为平均MOS晶体管的漏极和源极处的信号，并将平均信号提供给MOS晶体管的栅极以及与栅极耦合的一个或多个电流源; 电路被配置为改变栅极处的电压，以便改变MOS晶体管的电阻。 平均电路包括耦合在漏极和栅极之间的第一MOS电路，与漏极和栅极之间的第一MOS电路并联耦合的第一电容器，耦合在源极和栅极之间的第二MOS电路和第二电容器 在源极和栅极之间并联耦合到第二MOS电路。

公开(公告)号：US20150077070A1

公开(公告)日：2015-03-19

申请号：US14446815

申请日：2014-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shuaeb Fazeel ,  Eeshan Miglani ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/467 ,  G05F3/222 ,  G05F3/242

Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.

Abstract translation: 公开了一种提供电源噪声前馈消除的电压调节器。 电压调节器包括接收电源电压并产生比例电压的过程跟踪电路。 跟踪电容器耦合到过程跟踪电路，并基于比例电压产生注入电压。 Ahuja补偿稳压器产生调节电压。 在Ahuja补偿调节器的反馈路径上提供注入电压。

公开(公告)号：US12191877B2

公开(公告)日：2025-01-07

申请号：US17898844

申请日：2022-08-30

Applicant: Texas Instruments Incorporated

Inventor： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

公开(公告)号：US20240072820A1

公开(公告)日：2024-02-29

申请号：US17898844

申请日：2022-08-30

Applicant: Texas Instruments Incorporated

Inventor： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

CPC classification number: H03M1/1245 ,  H03M1/44 ,  H03M1/50 ,  H03M1/785

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

公开(公告)号：US11088702B2

公开(公告)日：2021-08-10

申请号：US16856167

申请日：2020-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi Soundararajan ,  Visvesvaraya Pentakota

IPC: H03M1/20

Abstract: A method of converting an analog signal to a digital code, comprising: using a first comparator to receive an input signal and a first comparison signal, and to generate a first output as a function of the input signal and the first comparison signal; using a second comparator to receive the input signal and a second comparison signal, and to generate a second output as a function of the input signal and the second comparison signal; and using an interpolation comparator to receive the first and second outputs, and to generate a third output based on relative timing of the first and second outputs; further including multiplexing to permit a second-level comparator to receive timing signals from the interpolation comparator and only one of two dummy comparators.

公开(公告)号：US10958258B2

公开(公告)日：2021-03-23

申请号：US16364239

申请日：2019-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi Soundararajan ,  Visvesvaraya Pentakota

IPC: H03K5/24 ,  H03M1/50 ,  H03K5/00 ,  H03M1/36 ,  H03M1/46 ,  H03M1/48

Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

公开(公告)号：US10911161B2

公开(公告)日：2021-02-02

申请号：US16697236

申请日：2019-11-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Oswal ,  Visvesvaraya Pentakota ,  Jagannathan Venkataraman ,  Jaiganesh Balakrishnan ,  Francesco Dantoni

IPC: H04B17/13 ,  H04B1/04 ,  H04L27/36

Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.

公开(公告)号：US10530378B1

公开(公告)日：2020-01-07

申请号：US16249927

申请日：2019-01-17

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Nagarajan Viswanathan ,  Visvesvaraya Pentakota

IPC: H03M1/06

Abstract: The disclosure provides a circuit. The circuit includes a zone detection block that generates a control signal in response to an input signal. An amplifier generates an amplified signal in response to the input signal and the control signal. An analog to digital converter (ADC) is coupled to the amplifier and samples the amplified signal to generate a digital signal. A digital corrector is coupled to the zone detection block and the ADC, and transforms the digital signal to generate a rectified signal based on the control signal and an error signal. An error estimator is coupled to the zone detection block and receives the rectified signal as a feedback. The error estimator generates the error signal in response to the control signal and the rectified signal.

公开(公告)号：US10483945B2

公开(公告)日：2019-11-19

申请号：US15852237

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish ,  Visvesvaraya Pentakota

IPC: H03H11/24 ,  H03H7/25 ,  H01F38/14 ,  H03K17/687 ,  H03G1/00 ,  H04B1/18 ,  H03G3/00 ,  H03G3/30

Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.

公开(公告)号：US20140084982A1

公开(公告)日：2014-03-27

申请号：US13627396

申请日：2012-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Visvesvaraya Pentakota

IPC: H03L5/00

CPC classification number: H03K17/16 ,  H03F1/32 ,  H03F3/45179 ,  H03F2203/45394 ,  H03F2203/45684 ,  H03F2203/45702 ,  H03K17/165

Abstract: Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate.

Abstract translation: 提供了构造成改善以线性区域工作的金属氧化物半导体（MOS）晶体管的二阶谐波失真的电路的各种实施例。 在一个实施例中，电路包括平均电路，其被配置为平均MOS晶体管的漏极和源极处的信号，并将平均信号提供给MOS晶体管的栅极以及与栅极耦合的一个或多个电流源; 电路被配置为改变栅极处的电压，以便改变MOS晶体管的电阻。 平均电路包括耦合在漏极和栅极之间的第一MOS电路，与漏极和栅极之间的第一MOS电路并联耦合的第一电容器，耦合在源极和栅极之间的第二MOS电路和第二电容器 在源极和栅极之间并联耦合到第二MOS电路。