公开(公告)号：US20200082055A1

公开(公告)日：2020-03-12

申请号：US16686448

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Yung Feng Chang

IPC: G06F17/50 ,  G03F1/36

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

公开(公告)号：US20200051972A1

公开(公告)日：2020-02-13

申请号：US16658389

申请日：2019-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi Lee ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Yung Feng Chang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  G06F17/50 ,  H01L21/3115 ,  H01L21/266 ,  H01L29/08

Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.

公开(公告)号：US10453837B2

公开(公告)日：2019-10-22

申请号：US16396447

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi Lee ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Yung Feng Chang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  G06F17/50 ,  H01L21/3115 ,  H01L21/266 ,  H01L29/08

Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.

公开(公告)号：US20190252370A1

公开(公告)日：2019-08-15

申请号：US16396447

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi Lee ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Yung Feng Chang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/3115 ,  H01L21/266 ,  H01L29/08 ,  G06F17/50

CPC classification number: H01L27/0266 ,  G06F17/5072 ,  H01L21/266 ,  H01L21/31155 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7851

Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.

公开(公告)号：US10276445B2

公开(公告)日：2019-04-30

申请号：US15692769

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Sheng Fan ,  Chun-Yen Lin ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

公开(公告)号：US09865589B1

公开(公告)日：2018-01-09

申请号：US15339282

申请日：2016-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Chi Lee ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Yung Feng Chang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/266 ,  H01L21/3115 ,  G06F17/50 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0266 ,  G06F17/5072 ,  H01L21/266 ,  H01L21/31155 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7851

Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.

公开(公告)号：US09859364B1

公开(公告)日：2018-01-02

申请号：US15448709

申请日：2017-03-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Hsiung Wang ,  Bao-Ru Young ,  Tung-Heng Hsieh

IPC: H01L21/82 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76843 ,  H01L23/535 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a source/drain feature, a gate structure, a top interlayer dielectric (ILD), a contact, and an isolation pillar. The source/drain feature is at least partially disposed in the substrate. The gate structure is disposed on the substrate and adjacent to the source/drain feature. The top ILD is disposed on the gate structure. The contact is disposed on the source/drain feature. The contact includes a barrier metal and a contact metal. The barrier metal is disposed on and in contact with the source/drain feature. The contact metal is disposed on the barrier metal. The isolation pillar is disposed adjacent to the contact. The isolation pillar is in contact with the barrier metal and the contact metal of the contact and the top ILD.

公开(公告)号：US20150364575A1

公开(公告)日：2015-12-17

申请号：US14835958

申请日：2015-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

公开(公告)号：US12300696B2

公开(公告)日：2025-05-13

申请号：US18358594

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Sheng Fan ,  Bao-Ru Young ,  Tung-Heng Hsieh

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

公开(公告)号：US11742244B2

公开(公告)日：2023-08-29

申请号：US17093350

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Sheng Fan ,  Chun-Yen Lin ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L29/6681 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.