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    Photodiode gate dielectric protection layer
    24.
    发明授权
    Photodiode gate dielectric protection layer 有权
    光电二极管介质保护层

    公开(公告)号：US09147710B2

    公开(公告)日：2015-09-29

    申请号：US13948217

    申请日：2013-07-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

    IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146 ,  H01L31/18

    CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

    Abstract: The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.

    Abstract translation: 本公开涉及一种方法，本公开涉及一种有源像素传感器，其具有栅极介电保护层，其在制造期间减小对下面的栅极介电层的损伤，以及相关联的形成方法。 在一些实施例中，有源像素传感器具有设置在半导体衬底内的光电检测器。 具有第一栅极结构的转移晶体管位于设置在半导体衬底之上的第一栅极电介质层上。 具有第二栅极结构的复位晶体管位于第一栅极介电层上。 在第一栅极结构和第二栅极结构之间并且在光电检测器上方的位置处，在栅极氧化物上设置栅极介电保护层。 栅极介质保护层在制造有源像素传感器期间保护第一栅极介电层免受蚀刻过程。

    3DIC STRUCTURE AND METHODS OF FORMING
    25.
    发明公开
    3DIC STRUCTURE AND METHODS OF FORMING 审中-公开

    公开(公告)号：US20230154898A1

    公开(公告)日：2023-05-18

    申请号：US18156848

    申请日：2023-01-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Ming Wu ,  Yung-Lung Lin ,  Zhi-Yang Wang ,  Sheng-Chau Chen ,  Cheng-Hsien Chou

    IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

    CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L24/06 ,  H01L24/02

    Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

    IMAGE SENSOR SCHEME FOR OPTICAL AND ELECTRICAL IMPROVEMENT
    29.
    发明申请
    IMAGE SENSOR SCHEME FOR OPTICAL AND ELECTRICAL IMPROVEMENT 有权

    公开(公告)号：US20210225919A1

    公开(公告)日：2021-07-22

    申请号：US17219960

    申请日：2021-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Keng-Yu Chou ,  Yeur-Luen Tu

    IPC: H01L27/146

    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a photodetector arranged within a substrate. The substrate has surfaces defining one or more protrusions arranged along a first side of the substrate over the photodetector. One or more isolation structures are arranged within one or more trenches defined by sidewalls of the substrate arranged on opposing sides of the photodetector. The one or more trenches extend from the first side of the substrate to within the substrate. The one or more isolation structures respectively include a reflective medium configured to reflect electromagnetic radiation.

    Deep trench isolation shrinkage method for enhanced device performance
    30.
    发明授权
    Deep trench isolation shrinkage method for enhanced device performance 有权

    公开(公告)号：US10964746B2

    公开(公告)日：2021-03-30

    申请号：US16405102

    申请日：2019-05-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

    IPC: H01L27/146 ,  H01L33/20 ,  H01L21/8238

    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

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